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| PRELIMINARY DATA SHEET MICRONAS VPC 323xD Comb Filter Video Processor Edition July 26, 2001 6251-472-1PD MICRONAS VPC 323xD Contents Page 5 5 6 7 8 8 8 8 8 8 8 8 9 9 10 10 10 11 11 11 11 12 13 13 13 13 13 13 14 14 14 14 15 15 15 15 16 16 16 17 17 17 17 17 18 18 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.1.5. 2.1.6. 2.2. 2.3. 2.3.1. 2.3.2. 2.3.3. 2.3.4. 2.3.5. 2.3.6. 2.3.7. 2.3.8. 2.3.9. 2.3.10. 2.4. 2.4.1. 2.4.2. 2.4.3. 2.4.4. 2.4.4.1. 2.4.4.2. 2.4.4.3. 2.4.5. 2.4.6. 2.5. 2.5.1. 2.5.2. 2.5.3. 2.5.4. 2.6. 2.7. 2.8. 2.9. 2.9.1. 2.9.2. 2.9.3. Title Introduction System Architecture Video Processor Family VPC Applications Functional Description Analog Video Front-End Input Selector Clamping Automatic Gain Control Analog-to-Digital Converters Digitally Controlled Clock Oscillator Analog Video Output Adaptive Comb Filter Color Decoder IF-Compensation Demodulator Chrominance Filter Frequency Demodulator Burst Detection / Saturation Control Color Killer Operation Automatic standard recognition PAL Compensation /1-H Comb Filter Luminance Notch Filter Skew Filtering Component Interface Processor CIP Component Analog Front-End Matrix Component YCrCb Control Softmixer Static Switch Mode Static Mixer Mode Dynamic Mixer Mode 4:4:4 to 4:2:2 Downsampling Fast Blank and Signal Monitoring Horizontal Scaler Horizontal Lowpass-filter Horizontal Prescaler Horizontal Scaling Engine Horizontal Peaking-filter Vertical Scaler Contrast and Brightness Blackline Detector Control and Data Output Signals Line-Locked Clock Generation Sync Signals DIGIT3000 Output Format PRELIMINARY DATA SHEET 2 Micronas PRELIMINARY DATA SHEET VPC 323xD Contents, continued Page 18 18 18 20 20 20 20 20 22 24 24 25 25 29 29 29 29 29 30 31 31 32 32 32 53 53 55 55 55 58 61 62 64 64 64 65 66 66 66 66 67 68 68 Section 2.9.4. 2.9.5. 2.9.6. 2.9.7. 2.9.8. 2.9.9. 2.10. 2.10.1. 2.11. 2.12. 2.12.1. 2.12.2. 2.12.3. 2.12.4. 2.12.5. 2.12.6. 2.12.7. 2.12.8. 2.12.9. 2.12.10. 2.12.11. 3. 3.1. 3.2. 3.2.1. 3.2.2. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.3. 4.6.4. 4.6.4.1. 4.6.4.2. 4.6.4.3. 4.6.4.4. 4.6.4.5. 4.6.4.6. Title Line-Locked 4:2:2 Output Format Line-Locked 4:1:1 Output Format ITU-R 656 Output Format Output Code Levels Output Ports Test Pattern Generator PAL+ Support Output Signals for PAL+/Color+ Support Video Sync Processing Picture in Picture (PIP) Processing and Control Configurations PIP Display Modes Predefined Inset Picture Size Acquisition and Display Window Frame and Background Color Vertical Shift of the Main Picture Free Running Display Mode Frame and Field Display Mode External Field Memory Field-Buffer-Extension Mode Double-Windows-Extension Mode Serial Interface I2C-Bus Interface Control and Status Registers Calculation of Vertical and East-West Deflection Coefficients Scaler Adjustment Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions (pin numbers for PQFP80 package) Pin Configuration Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Recommended Crystal Characteristics Characteristics Characteristics, 5 MHz Clock Output Characteristics, 20 MHz Clock Input/Output, External Clock Input (XTAL1) Characteristics, Reset Input, Test Input, VGAV Input, YCOEQ Input Characteristics, Power-up Sequence Characteristics, FPDAT Input/Output Characteristics, I2C Bus Interface Micronas 3 VPC 323xD Contents, continued Page 68 69 69 71 72 75 76 78 79 80 80 80 82 82 82 83 84 Section 4.6.4.7. 4.6.4.8. 4.6.4.9. 4.6.4.10. 4.6.4.11. 4.6.4.12. 4.6.4.13. 5. 5.1. 5.2. 5.2.1. 5.2.2. 5.2.3. 5.2.3.1. 5.2.3.2. 5.2.3.3. 6. Title Characteristics, I2C Bus Address Select I2CSEL Input Characteristics, Analog Video and Component Inputs Characteristics, Analog Front-End and ADCs Characteristics, Analog FB Input Characteristics, Output Pin Specification Characteristics, Input Pin Specification Characteristics, Clock Output Specification Application Circuit Application Note: VGA mode with VPC 323xD Application Note: PIP Mode Programming Procedure to Program a PIP Mode I2C Registers Programming for PIP Control Examples Select Predefined Mode 2 Select a Strobe Effect in Expert Mode Select Predefined Mode 6 for Tuner Scanning Data Sheet History PRELIMINARY DATA SHEET 4 Micronas PRELIMINARY DATA SHEET VPC 323xD Comb Filter Video Processor 1. Introduction The VPC 323xD is a high-quality, single-chip video front-end, which is targeted for 4:3 and 16:9, 50/60-Hz and 100/120 Hz TV sets. It can be combined with other members of the DIGIT3000 IC family (such as DDP 331x) and/or it can be used with 3rd-party products. The main features of the VPC 323xD are - high-performance adaptive 4H comb filter Y/C separator with adjustable vertical peaking - multi-standard color decoder PAL/NTSC/SECAM including all substandards - four CVBS, one S-VHS input, one CVBS output - two RGB/YCrCb component inputs, one Fast Blank (FB) input - integrated high-quality A/D converters and associated clamp and AGC circuits - multi-standard sync processing - linear horizontal scaling (0.25 ... 4), as well as non-linear horizontal scaling `Panoramavision' - PAL+ preprocessing - line-locked clock, data and sync, or 656-output interface - peaking, contrast, brightness, color saturation and tint for RGB/ YCrCb and CVBS/S-VHS - high-quality soft mixer controlled by Fast Blank 1 -- --- PIP processing for four picture sizes ( 1, 1, ------ , or 4 9 16 1 --- of normal size) with 8-bit resolution 36 - 15 predefined PIP display configurations and expert mode (fully programmable) - control interface for external field memory - I2C-bus interface - one 20.25-MHz crystal, few external components - 80-pin PQFP package 1.1. System Architecture Fig.1-1 shows the block diagram of the video processor CIN VIN1 VIN2 VIN3 VIN4 VOUT Analog Front-end Adaptive Comb Filter NTSC PAL Color Decoder NTSC PAL SECAM Saturation Tint Y Mixer Y 2D Scaler PIP Panorama Mode Contrast Brightness Output Formatter ITU-R 656 ITU-R 601 Memory Control Y OUT CrCb OUT YCOE FIFO CNTL Cr Cr AGC 2xADC Cb Cb Peaking RGB/ YCrCb FB RGB/ YCrCb Processing Y Analog Component U/B Cr Matrix Front-End Contrast V/R Saturation Cb Brightness 4 x ADC FB FB Tint Y/G I2C Bus Clock Gen. Sync + Clock Generation LL Clock H Sync V Sync AVO 20.25 MHz I2C Bus Fig. 1-1: Block diagram of the VPC 323xD Micronas 5 VPC 323xD 1.2. Video Processor Family The VPC video processor family supports 15 /32-kHz systems and is available with different comb filter options. Table 1-1 gives an overview of the VPC video processor family. PRELIMINARY DATA SHEET Table 1-1: VPC Processor Family for 100 Hz, Double-Scan and Line-Locked Clock Applications Features Type Adaptive Combfilter (PAL/NTSC) 4H Panorama Vision 4H 4H 2H Analog Component Inputs 2 2 Vertical Scaler (PIP) Digital Output Interface ITU-R 601, ITU-R 656 ITU-R 601, ITU-R 656 ITU-R 601, ITU-R 656 ITU-R 601, ITU-R 656 ITU-R 601 ITU-R 601 ITU-R 601 VPC 3230D VPC 3231D VPC 3232D VPC 3233D VPC 3215C VPC 3210A VPC 3211A 6 Micronas PRELIMINARY DATA SHEET VPC 323xD external sources, such as MPEG-2 set-top boxes in transparent (4:2:2) quality. Furthermore, it transforms RGB/Fast Blank signals to the common digital video bus and makes those signals available for 100-Hz upconversion or double-scan processing. In some European countries (Italy), this feature is mandatory. SRC (e. g. SDA 94xx from Micronas) indicates memory based image processing, such as scan rate conversion, vertical processing (Zoom), or PAL+ reconstruction. The VPC supports memory-based applications through line-locked clocks, syncs, and data. Additionally, the VPC 323xD provides a 656-output interface and FIFO control signals. Examples: 1.3. VPC Applications Fig. 1-2 depicts several VPC applications. Since the VPC functions as a video front-end, it must be complemented with additional functionality to form a complete TV set. The DDP 331x contains the video back-end with video postprocessing (contrast, peaking, CTI,...), H/V-deflection, RGB insertion (SCART, Text, PIP,...) and tube control (cutoff, white-drive, beam current limiter). It generates a beam scan velocity modulation output from the digital YCrCb and RGB signals. Note, that this signal is not generated from the external analog RGB inputs. The component interface of the VPC 323xD provides a high-quality analog RGB interface with character insertion capability. It also allows appropriate processing of - Europe: 15 kHz/50 Hz 32 kHz/100 Hz interlaced - US: 15 kHz/60 Hz 32 kHz/60 Hz non-interlaced a) YCrCb/RGBFB CVBS VPC 323xD FIFO YCrCb/RGBFB CVBS RGB VPC 323xD DDP 331x RGB H/V Defl. RGB H/V Defl. RGB H/V Defl. b) YC rC b CVBS VPC 323xD SRC DDP 331x c) YCrCb/RGBFB CVBS VPC 323xD SRC DDP 331x Fig. 1-2: VPC 32xxD applications a) 15-kHz application Europe b) double-scan application (US, Japan) with YCrCb inputs c) 100-Hz application (Europe) with RGBFB inputs Micronas 7 VPC 323xD 2. Functional Description 2.1. Analog Video Front-End This block provides the analog interfaces to all video inputs and mainly carries out analog-to-digital conversion for the following digital video processing. A block diagram is given in Fig. 2-1. Most of the functional blocks in the front-end are digitally controlled (clamping, AGC, and clock-DCO). The control loops are closed by the Fast Processor (`FP') embedded in the decoder. PRELIMINARY DATA SHEET 2.1.3. Automatic Gain Control A digitally working automatic gain control adjusts the magnitude of the selected baseband by +6/-4.5 dB in 64 logarithmic steps to the optimal range of the ADC. The gain of the video input stage including the ADC is 213 steps/V with the AGC set to 0 dB. 2.1.4. Analog-to-Digital Converters Two ADCs are provided to digitize the input signals. Each converter runs with 20.25 MHz and has 8 bit resolution. An integrated bandgap circuit generates the required reference voltages for the converters. The two ADCs are of a 2-stage subranging type. 2.1.1. Input Selector Up to five analog inputs can be connected. Four inputs are for composite video or S-VHS luma signal. These inputs are clamped to the sync back porch and are amplified by a variable gain amplifier. One input is for connection of S-VHS carrier chrominance signal. This input is internally biased and has a fixed gain amplifier. A second S-VHS chroma signal can be connected to video-input VIN1. 2.1.5. Digitally Controlled Clock Oscillator The clock generation is also a part of the analog front end. The crystal oscillator is controlled digitally by the control processor; the clock frequency can be adjusted within 150 ppm. 2.1.6. Analog Video Output 2.1.2. Clamping The composite video input signals are AC coupled to the IC. The clamping voltage is stored on the coupling capacitors and is generated by digitally controlled current sources. The clamping level is the back porch of the video signal. S-VHS chroma is also AC coupled. The input pin is internally biased to the center of the ADC input range. The input signal of the Luma ADC is available at the analog video output pin. The signal at this pin must be buffered by a source follower. The output voltage is 2 V, thus the signal can be used to drive a 75 line. The magnitude is adjusted with an AGC in 8 steps together with the main AGC. Analog Video Output CVBS/Y CVBS/Y CVBS/Y CVBS/Y/C C VIN4 VIN3 VIN2 VIN1 CIN input mux clamp gain bias AGC +6/-4.5 dB ADC digital CVBS or Luma ADC digital Chroma system clocks reference generation frequency DVCO 150 ppm 20.25 MHz Fig. 2-1: Analog front-end 8 Micronas PRELIMINARY DATA SHEET VPC 323xD HDG typically defines the comb strength on horizontal edges. It determines the amount of the remaining cross-luminance and the sharpness on edges respectively. As HDG increases, the comb strength, e. g. cross luminance reduction and sharpness, increases. VDG typically determines the comb filter behavior on vertical edges. As VDG increases, the comb strength, e. g. the amount of hanging dots, decreases. After selecting the combfilter performance in horizontal and vertical direction, the diagonal picture performance may further be optimized by adjusting DDR. As DDR increases, the dot crawl on diagonal colored edges is reduced. To enhance the vertical resolution of the picture, the VPC provides a vertical peaking circuitry. The filter gain is adjustable between 0 - +6 dB and a coring filter suppresses small amplitudes to reduce noise artifacts. In relation to the comb filter, this vertical peaking widely contributes to an optimal two-dimensional resolution homogeneity. 2.2. Adaptive Comb Filter The 4H adaptive comb filter is used for high-quality luminance/chrominance separation for PAL or NTSC composite video signals. The comb filter improves the luminance resolution (bandwidth) and reduces interferences like cross-luminance and cross-color. The adaptive algorithm eliminates most of the mentioned errors without introducing new artifacts or noise. A block diagram of the comb filter is shown in Fig. 2-2. The filter uses four line delays to process the information of three video lines. To have a fixed phase relationship of the color subcarrier in the three channels, the system clock (20.25 MHz) is fractionally locked to the color subcarrier. This allows the processing of all color standards and substandards using a single crystal frequency. The CVBS signal in the three channels is filtered at the subcarrier frequency by a set of bandpass/notch filters. The output of the three channels is used by the adaption logic to select the weighting that is used to reconstruct the luminance/chrominance signal from the 4 bandpass/notch filter signals. By using soft mixing of the 4 signals switching artifacts of the adaption algorithm are completely suppressed. The comb filter uses the middle line as reference, therefore, the comb filter delay is two lines. If the comb filter is switched off, the delay lines are used to pass the luma/chroma signals from the A/D converters to the luma/chroma outputs. Thus, the processing delay is always two lines. In order to obtain the best-suited picture quality, the user has the possibility to influence the behavior of the adaption algorithm going from moderate combing to strong combing. Therefore, the following three parameters may be adjusted: - HDG (horizontal difference gain) - VDG (vertical difference gain) - DDR (diagonal dot reducer) 2.3. Color Decoder In this block, the standard luma/chroma separation and multi-standard color demodulation is carried out. The color demodulation uses an asynchronous clock, thus allowing a unified architecture for all color standards. A block diagram of the color decoder is shown in Fig. 2-4. The luma as well as the chroma processing, is shown here. The color decoder also provides several special modes, e.g. wide band chroma format which is intended for S-VHS wide bandwidth chroma. Also, filter settings are available for processing a PAL+ helper signal. If the adaptive comb filter is used for luma chroma separation, the color decoder uses the S-VHS mode processing. The output of the color decoder is YCrC b in a 4:2:2 format. Luma / Chroma Mixers Adaption Logic Bandpass Filter CVBS Input 2H Delay Line Bandpass/ Notch Filter Luma Output Chroma Output 2H Delay Line Chroma Input Bandpass Filter Fig. 2-2: Block diagram of the adaptive comb filter (PAL mode) Micronas 9 VPC 323xD 2.3.1. IF-Compensation With off-air or mistuned reception, any attenuation at higher frequencies or asymmetry around the color subcarrier is compensated. Four different settings of the IF-compensation are possible (see Fig. 2-3): - flat (no compensation) - 6 dB/octave - 12 dB/octave - 10 dB/MHz The last setting gives a very large boost to high frequencies. It is provided for SECAM signals that are decoded using a SAW filter specified originally for the PAL standard. 2.3.2. Demodulator PRELIMINARY DATA SHEET The entire signal (which might still contain luma) is quadrature-mixed to the baseband. The mixing frequency is equal to the subcarrier for PAL and NTSC, thus achieving the chroma demodulation. For SECAM, the mixing frequency is 4.286 MHz giving the quadrature baseband components of the FM modulated chroma. After the mixer, a lowpass filter selects the chroma components; a downsampling stage converts the color difference signals to a multiplexed half rate data stream. The subcarrier frequency in the demodulator is generated by direct digital synthesis; therefore, substandards such as PAL 3.58 or NTSC 4.43 can also be demodulated. dB 2.3.3. Chrominance Filter The demodulation is followed by a lowpass filter for the color difference signals for PAL/NTSC. SECAM requires a modified lowpass function with bell filter characteristic. At the output of the lowpass filter, all luma information is eliminated. The lowpass filters are calculated in time multiplex for the two color signals. Three bandwidth settings (narrow, normal, broad) are available for each standard (see Fig. 2-5). For PAL/NTSC, a wide band chroma filter can be selected. This filter is intended for high bandwidth chroma signals, e.g. a nonstandard wide bandwidth S-VHS signal. MHz Fig. 2-3: Frequency response of chroma IF-compensation Luma / CVBS Notch Filter Luma MUX 1 H Delay CrossSwitch Chroma ACC MUX IF Compensation MIXER DC-Reject Lowpass Filter Phase/Freq Demodulator Chroma ColorPLL/ColorACC Fig. 2-4: Color decoder 10 Micronas PRELIMINARY DATA SHEET VPC 323xD color killer operation; they are used for automatic standard detection as well. dB 2.3.6. Color Killer Operation The color killer uses the burst-phase /burst-frequency measurement to identify a PAL/NTSC or SECAM color signal. For PAL/NTSC, the color is switched off (killed) as long as the color subcarrier PLL is not locked. For SECAM, the killer is controlled by the toggle of the burst frequency. The burst amplitude measurement is used to switch off the color if the burst amplitude is below a programmable threshold. Thus, color will be killed for very noisy signals. The color amplitude killer has a programmable hysteresis. PAL/NTSC dB MHz 2.3.7. Automatic Standard Recognition The burst-frequency measurement is also used for automatic standard recognition (together with the status of horizontal and vertical locking) thus allowing a completely independent search of the line and color standard of the input signal. The following standards can be distinguished: PAL B,G,H,I; NTSC M; SECAM; NTSC 44; PAL M; PAL N; PAL 60 For a preselection of allowed standards, the recognition can be enabled/disabled via I2C bus for each standard separately. If at least one standard is enabled, the VPC 323xD checks regularly the horizontal and vertical locking of the input signal and the state of the color killer. If an error exists for several adjacent fields a new standard search is started. Depending on the measured line number and burst frequency the current standard is selected. For error handling, the recognition algorithm delivers the following status information: - search active (busy) - search terminated, but failed - found standard is disabled - vertical standard invalid The ACC has a control range of +30 ... -6 dB. Color saturation is adjustable independently of the color standard. In PAL/NTSC it is used as reference for the ACC. In SECAM the necessary gains are calculated automatically. For SECAM decoding, the frequency of the burst is measured. Thus, the current chroma carrier frequency can be identified and is used to control the SECAM processing. The burst measurements also control the - no color found SECAM MHz Fig. 2-5: Frequency response of chroma filters 2.3.4. Frequency Demodulator The frequency demodulator for demodulating the SECAM signal is implemented as a CORDIC-structure. It calculates the phase and magnitude of the quadrature components by coordinate rotation. The phase output of the CORDIC processor is differentiated to obtain the demodulated frequency. After the deemphasis filter, the Dr and Db signals are scaled to standard C rCb amplitudes and fed to the crossover-switch. 2.3.5. Burst Detection / Saturation Control In the PAL/NTSC system the burst is the reference for the color signal. The phase and magnitude outputs of the CORDIC are gated with the color key and used for controlling the phase-locked loop (APC) of the demodulator and the automatic color control (ACC) in PAL/ NTSC. Micronas 11 VPC 323xD 2.3.8. PAL Compensation/1-H Comb Filter The color decoder uses one fully integrated delay line. Only active video is stored. The delay line application depends on the color standard: - NTSC: - PAL: 1-H comb filter or color compensation color compensation CVBS 8 Notch filter Chroma Process. PRELIMINARY DATA SHEET Y Cr C b Luma 8 Y Chroma Process. chroma 8 CrC b a) conventional CVBS 8 Notch filter b) S-VHS Y - SECAM: crossover switch Chroma Process. 1H Delay Cr C b In the NTSC compensated mode, Fig. 2-6 c), the color signal is averaged for two adjacent lines. Thus, cross-color distortion and chroma noise is reduced. In the NTSC 1-H comb filter mode, Fig. 2-6 d), the delay line is in the composite signal path, thus allowing reduction of cross-color components, as well as cross-luminance. The loss of vertical resolution in the luminance channel is compensated by adding the vertical detail signal with removed color information. If the 4H adaptive comb filter is used, the 1-H NTSC comb filter has to be deselected. c) compensated CVBS 8 1H Delay Notch filter Y Chroma Process. CrC b d) comb filter Fig. 2-6: NTSC color decoding options CVBS 8 Notch filter Y Chroma Process. 1H Delay CrC b a) conventional Luma 8 Y Chroma 8 Chroma Process. 1H Delay Cr C b b) S-VHS Fig. 2-7: PAL color decoding options CVBS 8 Notch filter Y Chroma Process. 1H Delay MUX CrC b Fig. 2-8: SECAM color decoding 12 Micronas PRELIMINARY DATA SHEET VPC 323xD 2.4. Component Interface Processor CIP This block (see Fig. 2-10) contains all the necessary circuitry dedicated to external analog components (YCrCb_cip) such as RGB or YCrCb signals from DVD players, or other RGB sources with Fast Blank for real time insertion on the main picture (YCrCb_main). 2.4.1. Component Analog Front-End VPC 323xD provides two analog RGB/YCrCb input ports, one with Fast Blank capability and one without. Analog component signals contain high-frequency components (e. g. OSD) and/or high-frequency clock residues. Thus, it is recommended to implement analog anti-alias low-pass filters on each input, including FB (e. g. -3 dB at 5...6 MHz). While all signals are coupled by 220 nF clamping capacitors, the Fast Blank input requires DC coupling. 2.3.9. Luminance Notch Filter If a composite video signal is applied, the color information is suppressed by a programmable notch filter. The position of the filter center frequency depends on the subcarrier frequency for PAL/NTSC. For SECAM, the notch is directly controlled by the chroma carrier frequency. This considerably reduces the cross-luminance. The frequency responses for all three systems are shown in Fig. 2-9. 10 dB 0 -10 -20 -30 -40 0 2 4 6 8 10 MHz PAL/NTSC notch filter 10 dB The selected signal channel is further converted into a digital form by three high-quality ADCs running at 20.25 MHz with a resolution of 8 bit. The FB input is digitized with a resolution of 6 bit. Note: The VPC 323xD is synchronized always by the main CVBS/Y ADC input. In component mode, the sync signal has to be fed to this input accordingly. 0 -10 -20 -30 2.4.2. Matrix 0 2 4 6 8 10 MHz -40 SECAM notch filter Fig. 2-9: Frequency responses of the luma notch filter for PAL, NTSC, SECAM The RGB signals are converted to the YCrCb format by a matrix operation: Y = 0.299R + 0.587G + 0.114B (R-Y)= 0.701R - 0.587G - 0.114B (B-Y)=-0.299R - 0.587G + 0.886B In case of YCrCb input the matrix is bypassed. 2.4.3. Component YCrCb Control The VPC 323xD supports the following picture adjustment parameters on the component signal: - 0 contrast 63/32 - -128 brightness 127 - 0 saturation Cr 63/32 - 0 saturation Cb 63/32 - -20 tint 20 degrees 2.3.10. Skew Filtering The system clock is free-running and not locked to the TV line frequency. Therefore, the ADC sampling pattern is not orthogonal. The decoded YCrCb signals are converted to an orthogonal sampling raster by the skew filters, which are part of the scaler block. The skew filters are controlled by a skew parameter and allow the application of a group delay to the input signals without introducing waveform or frequency response distortion. The amount of phase shift of this filter is controlled by the horizontal PLL1. The accuracy of the filters is 1/32 clocks for luminance and 1/4 clocks for chroma. Thus the 4:2:2 YCrCb data is in an orthogonal pixel format even in the case of nonstandard input signals such as VCR. Micronas 13 VPC 323xD Table 2-1 shows the settings to achieve exact level matching between YCrCb_cip and YCrCb_main channel. Table 2-1: Standard picture settings PRELIMINARY DATA SHEET The factor k is clamped to 0 or 64, hence selecting YCrCb_main or the component input YCrCb_cip (see Table 2-2). 2.4.4.2. Static Mixer Mode input format RGB YCrCb contrast 27 27 brightness 68 68 satCr 29 40 satCb 23 40 The signal YCrCb_main and the component signal YCrCb_cip may also be statically mixed. In this environment, k is manually controlled via I2C registers FBGAIN and FBOFFS according to the following expression: k = FBGAIN*(31-FBOFFS) + 32 All the necessary limitation and rounding operation are built-in to fit the range: 0 k 64. In the static mixer mode as well as in the previously mentioned static switch mode (see Table 2-2), the softmixer operates independently of the analog Fast Blank input. Note: R, G, B, Cr, Cb, = 0.7 Vpp, Y(+ sync) 1 Vpp 2.4.4. Softmixer After an automatic delay matching, the component signals and the upsampled main video signal are gathered onto a unique YCrCb channel by means of a versatile 4:4:4 softmixer (see also Fig. 2-10). The softmixer circuit consists of a Fast Blank (FB) processing block supplying a mixing factor k (0...64) to a high quality signal mixer achieving the output function: YCrCb_mix=( k*YCrCb_main+ (64-k)*YCrCb_cip )/64 The softmixer supports several basic modes that are selected via I2C bus (see Table 2-2). 2.4.4.3. Dynamic Mixer Mode In the dynamic mixer mode, the mixer is controlled by the Fast Blank signal. The VPC 323xD provides a linear mixing coefficient k=kl = FBGAIN*(FB-FBOFFS) + 32 (FB is the digitized Fast Blank), and a non-linear mixing coefficient knl=F(kl), which results from a further non-linear processing of kl. While the linear mixing coefficient is used to insert a full-screen video signal, the non-linear coefficient is well-suited to insert Fast Blank related signals like text. The non-linear mixing reduces disturbing effects like over/undershoots at critical Fast Blank edges. 2.4.4.1. Static Switch Mode In its simplest and most common application the softmixer is used as a static switch between YCrCb_main and YCrCb_cip. This is for instance the adequate way to handle a DVD component signal. mixer YCrCb_main VIDEO Y/C processing YCrCb_mix YCrCb_cip RGB/YCrCb Component Processing Fig. 2-10: Block diagram of the component mixer 14 Micronas PRELIMINARY DATA SHEET VPC 323xD Table 2-2: CIP softmixer modes analog fast blank input I2C CIP mode Force YCrCb main Force RGB/ YCrCb Static Mixer FB Linear FB nonLinear SELLIN RGB DLY FBCLP FB MODE reading I2C register <27> <27>FBLSTAT <27>FBLRISE <27>FBLFALL 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 0 0 0 0 0 0 x 11 <27>FBLHIGH Fig. 2-11: Fast Blank Monitor 0 0 x x0 An additional monitoring bit is also provided for the RGB/YCrCb signal; it indicates whether the ADCs inputs are clipped or not. In case of clipping conditions (1Vpp RGB input for example) the ADC range can be extended by 3db by using the XAR bit. - CLIPD: set by RGB/YC rCb input clip, reset by register read 0 0 1 0 0 1 1 0 0 01 01 01 2.5. Horizontal Scaler The 4:2:2 YCrCb signal from the mixer output is processed by the horizontal scaler. It contains a lowpass filter, a prescaler, a scaling engine and a peaking filter. The scaler block allows a linear or nonlinear horizontal scaling of the input signal in the range of 1/32 to 4. Nonlinear scaling, also called "panorama vision", provides a geometrical distortion of the input picture. It is used to fit a picture with 4:3 format on a 16:9 screen by stretching the picture geometry at the borders. Also, the inverse effect - called water glass - can be produced by the scaler. A summary of scaler modes is given in Table 2-3. 2.4.5. 4:4:4 to 4:2:2 Downsampling After the mixer, the 4:4:4 YCrCb_mix data stream is downsampled to the 4:2:2 format. For this sake, a chroma lowpass filter is provided to eliminate high-frequency components above 5-6 Mhz which may typically be present on inserted high resolution RGB/ YCrCb sources. In case of main video processing (loop-through) only, it is recommended to bypass this filter by using the I2C bit CIPCFBY. 2.5.1. Horizontal Lowpass-filter 2.4.6. Fast Blank and Signal Monitoring The analog Fast Blank state is monitored by means of four I2C readable bits. These bits may be used by the TV controller for SCART signal ident: - FBHIGH: set by FB high, reset by register read at FB low - FBSTAT: FB status at register read - FBRISE: set by FB rising edge, reset by register read - FBFALL: set by FB falling edge, reset by register read The luma filter block applies anti-aliasing lowpass filters. The cutoff frequencies are selectable and have to be adapted to the horizontal scaling ratio. Micronas 15 VPC 323xD PRELIMINARY DATA SHEET dB 10 Table 2-3: Scaler modes Mode Scale Factor 0.75 linear nonlinear compr 1.33 linear Description 4:3 source displayed on a 16:9 tube, with side panels 4:3 source displayed on a 16:9 tube, Borders distorted Letterbox source (PAL+) displayed on a 4:3 tube, vertical overscan with cropping of side panels Letterbox source (PAL+) displayed on a 4:3 tube, vertical overscan, borders distorted, no cropping sample rate conversion to line-locked clock 0 -10 -20 Compression 4:3 16:9 Panorama 4:3 16:9 2 4 6 8 10 -30 -40 -50 MHz dB 10 Zoom 4:3 4:3 0 -10 Water glass 16:9 4:3 -20 nonlinear zoom -30 -40 20.25 13.5 MHz 1 2 3 4 5 0.66 -50 MHz Fig. 2-12: YCrCb downsampling lowpass-filter 2.5.2. Horizontal Prescaler To achieve a horizontal compression ratio between 1/4 and 1/32 (e. g. for double window or PIP operation) a linear downsampler resamples the input signal by 1 (=no presampling), 2, 4, and 8. 2.5.4. Horizontal Peaking-filter The horizontal scaler block offers an extra peaking filter for sharpness control. The center frequency of the peaking filter automatically adopts to the horizontal scaling ratio. Three center frequencies are selectable (see Fig. 2-13: ) - center at sampling rate / 2 - center at sampling rate / 4 - center at sampling rate / 6 2.5.3. Horizontal Scaling Engine The scaler contains a programmable decimation filter, a 1-H FIFO memory, and a programmable interpolation filter. The scaler input filter is also used for pixel skew correction, see 2.3.10. The decimator/interpolator structure allows optimal use of the FIFO memory. It allows a linear or nonlinear horizontal scaling of the input video signal in the range of 0.25 to 4. The controlling of the scaler is done by the internal Fast Processor. The filter gain is adjustable between 0 - +10 dB and a coring filter suppresses small amplitudes to reduce noise artifacts. 16 Micronas PRELIMINARY DATA SHEET VPC 323xD amplitude, the external controller reads this register, calculates the vertical scaling coefficient and transfers the new settings, e.g. vertical sawtooth parameters, horizontal scaling coefficient etc., to the VPC. Letterbox signals containing logos on the left or right side of the black areas are processed as black lines, while subtitles, inserted in the black areas, are processed as non-black lines. Therefore the subtitles are visible on the screen. To suppress the subtitles, the vertical zoom coefficient is calculated by selecting the larger number of black lines only. Dark video scenes with a low contrast level compared to the letterbox area are indicated by the BLKPIC bit. dB 20 15 10 5 0 -5 -10 0.1 0.2 0.3 0.4 0.5 LLC1/MHz Fig. 2-13: Peaking characteristics 2.9. Control and Data Output Signals The VPC 323xD supports two output modes: In DIGIT3000 mode, the output interfaces run at the main system clock, in line-locked mode, the VPC generates an asynchronous line-locked clock that is used for the output interfaces. The VPC delivers either a YCrC b 4:2:2 or a YCrC b 4:1:1 data stream, each with separate sync information. In case of YCrCb 4:2:2 format, the VPC 323xD also provides an interface with embedded syncs according to ITU-R656. 2.6. Vertical Scaler For PIP operation, the vertical scaler compresses the incoming 4:2:2 YCrCb active video signal in vertical direction. It supports a vertical compression ratio of 1(= no compression), 2, 3, 4 and 6. In case of a vertical compression of 2, 4 and 6, the filter performs the PAL compensation automatically and the standard PAL delay line should be bypassed (see 2.3.8.). 2.9.1. Line-Locked Clock Generation An on-chip rate multiplier is used to synthesize any desired output clock frequency of 13.5/16/18 MHz. A double clock frequency output is available to support 100 Hz systems. The synthesizer is controlled by the embedded RISC controller, which also controls all front-end loops (clamp, AGC, PLL1, etc.). This allows the generation of a line-locked output clock regardless of the system clock (20.25 MHz) which is used for comb filter operation and color decoding. The control of scaling and output clock frequency is kept independent to allow aspect ratio conversion combined with sample rate conversion. The line-locked clock circuity generates control signals, e.g. horizontal/vertical sync, active video output, it is also the interface from the internal (20.25 MHz) clock to the external line-locked clock system. If a line-locked clock is not required, i.e. in the DIGIT3000 mode, the system runs at the 20.25 MHz main clock. The horizontal timing reference in this mode is provided by the front-sync signal. In this case, the line-locked clock block and all interfaces run from the 20.25 MHz main clock. The synchronization signals from the line-locked clock block are still available, but for every line the internal counters are reset with the main-sync signal. A double clock signal is not available in DIGIT3000 mode. 2.7. Contrast and Brightness The VPC 323xD provides a selectable contrast and brightness adjustment for the luma samples. The control ranges are: - 0 contrast 63/32 - -128 brightness 127 Note: for ITU-R luma output code levels (16 ... 240), contrast has to be set to 48 and brightness has to be set to 16! 2.8. Blackline Detector In case of a letterbox format input video, e.g. Cinemascope, PAL+ etc., black areas at the upper and lower part of the picture are visible. It is suitable to remove or reduce these areas by a vertical zoom and/or shift operation. The VPC 323xD supports this feature by a letterbox detector. The circuitry detects black video lines by measuring the signal amplitude during active video. For every field the number of black lines at the upper and lower part of the picture are measured, compared to the previous measurement and the minima are stored in the I2C register BLKLIN. To adjust the picture Micronas 17 VPC 323xD 2.9.2. Sync Signals The front end will provide a number of sync/control signals which are output with the output clock. The sync signals are generated in the line-locked clock block. - Href: - AVO: - HC: - Vref: - INTLC: horizontal sync active video out (programmable) horizontal clamp (programmable) vertical sync interlace Luma Chroma C3 , C7 C2 , C6 C1 , C5 C0 , C4 note: C*xY Y1 Cb17 Cb16 Cr17 Cr16 PRELIMINARY DATA SHEET 2.9.5. Line-Locked 4:1:1 Output Format The orthogonal 4:1:1 output format is compatible to the industry standard. The YCrCb samples are skew-corrected and interpolated to an orthogonal sampling raster (see Table 2-5). Table 2-5: 4:1:1 Orthogonal output format Y2 Cb15 Cb14 Cr15 Cr14 Y3 Cb13 Cb12 Cr13 Cr12 Y4 Cb11 Cb10 Cr11 Cr10 All horizontal signals are not qualified with field information, i.e. the signals are present on all lines. The horizontal timing is shown in Fig. 2-16. Details of the horizontal/vertical timing are given in Fig. 2-20. Note: In the ITU-R656 compliant output format, the sync information is embedded in the data stream. (x = pixel number and y = bit number) 2.9.3. DIGIT3000 Output Format The picture bus format between all DIGIT3000 ICs is 4:2:2 YCrCb with 20.25 MHz samples/s. Only active video is transferred, synchronized by the system main sync signal (MSY) which indicates the start of valid data for each scan line and which initializes the color multiplex. The video data is orthogonally sampled YCrCb, the output format is given in Table 2-4. The number of active samples per line is 1080 for all standards (525 and 625). The output can be switched to 4:1:1 mode with the output format according to Table 2-5. Via the MSY line, serial data is transferred which contains information about the main picture such as current line number, odd/even field etc.). It is generated by the deflection circuitry and represents the orthogonal timebase for the entire system. Table 2-4: Orthogonal 4:2:2 output format Luma Chroma Y1 Cb1 Y2 C r1 Y3 Cb3 Y4 Cr3 2.9.6. ITU-R 656 Output Format This interface uses a YC rCb 4:2:2 data stream at a line-locked clock of 13.5 MHz. Luminance and chrominance information is multiplexed to 27 MHz in the following order: Cb1, Y1, Cr1, Y2, ... Timing reference codes are inserted into the data stream at the beginning and the end of each video line: - a `Start of active video'-Header (SAV) is inserted before the first active video sample - a `End of active video'-code (EAV) is inserted after the last active video sample. The incoming videostream is limited to a range of 1...254 since the data words 0 and 255 are used for identification of the reference headers. Both headers contain information about the field type and field blanking. The data words occurring during the horizontal blanking interval between EAV and SAV are filled with 0x10 for luminance and 0x80 for chrominance information. Table 2-6 shows the format of the SAV and EAV header. For activation of this output format, the following selections must be assured: - 13.5 MHz line locked clock - double-clock mode enabled 2.9.4. Line-Locked 4:2:2 Output Format In line-locked mode, the VPC 323xD provides the industry standard pixel stream for YCrC b data. The difference to DIGIT3000 native mode is only the number of active samples, which of course, depends on the chosen scaling factor. Thus, Table 2-4 is valid for both 4:2:2 modes. - ITU-R656-mode enabled - binary offset for Cr/Cb data Note that the following changes and extensions to the ITU-R656 standard have been included to support horizontal and vertical scaling: 18 Micronas PRELIMINARY DATA SHEET VPC 323xD Table 2-6: Coding of the SAV/EAV-header Bit No. Word MSB 7 First Second Third Fourth 1 0 0 T - Both the length and the number of active video lines varies with the selected window parameters. For compliance with the ITU-R656 recommendation, a size of 720 samples per line must be selected for each window. - During blanked video lines SAV/EAV headers are suppressed in pairs. To assure vertical sync detection the V-flag in the EAV header of the last active video line is set to 1. Additionally, during field blanking all SAV/EAV headers (with the V-flag set to 1) are inserted. LSB 6 1 0 0 F 5 1 0 0 V 4 1 0 0 H 3 1 0 0 P3 2 1 0 0 P2 1 1 0 0 P1 0 1 0 0 P0 F = 0 during field 1,F = 1 during field 2 V = 0 during active linesV = 1 during vertical field blanking H = 0 in SAV,H = 1 in EAV T = 1 (video task only) The bits P0, P1, P2, and P3 are Hamming-coded protection bits. dependent on window size 1728 samples Digital Video Output EAV SAV EAV SAV CB Y C R Y ... CB Y CR Y ... constant during horizontal blanking Y=10hex; CR=CB=80hex SAV: "start of active video" header EAV: "end of active video" header AVO Fig. 2-14: Output of video data with embedded reference headers (@27 MHz) Y DATA AVO LLC1 LLC2 80h 10h SAV1 SAV2 SAV3 SAV4 CB1 Y1 CR1 Y2 CBn-1 Yn-1 CRn-1 Yn EAV1 EAV2 EAV3 EAV4 80h 10h Fig. 2-15: Detailed data output (double-clock on) Micronas 19 VPC 323xD PRELIMINARY DATA SHEET Table 2-7: Output signals corresponding to the different formats Format 16 bit YCrCb422 8 bit YCrCb422 ITU-R 656 0 1 1 dblclk enable656 0 0 1 HSync PAL/NTSC PAL/NTSC not used VSync PAL/NTSC PAL/NTSC not used AVO marks active pixels marks active pixels not used Y-Data 4:2:2 4:2:2 ITU-R 656 C-Data 4:2:2 tri-stated tri-stated The multiplex of luminance and chrominance information and the embedding of 656-headers can be enabled independently. An overview of the resulting output formats and the corresponding signals is given in Table 2-7. - A/D conversion (shared with the existing ADCs) - mixing with subcarrier frequency - lowpass filter 2.5 MHz - gain control by chroma ACC - delay compensation to composite video path 2.9.7. Output Code Levels Output Code Levels correspond to ITU-R code levels: Y = 16...240 Black Level = 16 CrCb = 128112 An overview over the output code levels is given in Table 2-8. - output at the luma output port Helper signals are processed like the main video luma signals, i.e. they are subject to scaling, sample rate conversion and orthogonalization if activated. The adaptive comb filter processing is switched off for the helper lines. It is expected that further helper processing (e.g. nonlinear expansion, matched filter) is performed outside the VPC. 2.9.8. Output Ports All data and sync pins operate at TTL compliant levels and can be tri-stated via I2C registers. Additionally, the data outputs can be tri-stated via the YCOE output enable pin immediately. This function allows the digital insertion of a 2nd digital video source (e. g. MPEG aso.). To ensure optimum EMI performance data and clock outputs automatically adopt the driver strength depending on their specific external load (max. 50pF). Therefore no external resistors and/or inductors should be connected to these pins. Sync and Fifo control pins have to be adjusted manually via an I2C register. 2.10.1. Output Signals for PAL+/Color+ Support For a PAL+/Color+ signal, the 625 line PAL image contains a 16/9 core picture of 431 lines which is in standard PAL format. The upper and lower 72 lines contain the PAL+ helper signal, and line 23 contains signalling information for the PAL+ transmission. For PAL+ mode, the Y signal of the core picture, which is during lines 60-274 and 372-586, is replaced by the orthogonal composite video input signal. In order to fit the signal to the 8-bit port width, the ADC signal amplitudes are used. During the helper window, which is in lines 24-59, 275-310, 336-371, 587-622, the demodulated helper is signal processed by the horizontal scaler and the output circuitry. It is available at the luma output port. The processing in the helper reference lines 23 and 623 is different for the wide screen signaling part and the black reference and helper burst signals. The code levels are given in detail in Table 2-8, the output signal for the helper reference line is shown in Fig. 2- 17. 2.9.9. Test Pattern Generator The YCrCb outputs can be switched to a test mode where YCrCb data are generated digitally in the VPC 323xD. Test patterns include luma/chroma ramps, flat field and a pseudo color bar. 2.10. PAL+ Support For PAL+, the VPC 323xD provides basic helper preprocessing: 20 Micronas PRELIMINARY DATA SHEET VPC 323xD Table 2-8: Output signal code levels for a PAL/PAL+ signal Output Signal Output Format Standard YCrCb (100% Chroma) CVBS, CrCb binary 16 Luma Outputs Y[7:0] Black/Zero Level Amplitude 224 Chroma Outputs C[7:0] Output Format offset binary signed binary 64 149 (luma) offset binary signed Demodulated Helper Helper WSS Helper black level, Ref. Burst signed binary offset binary 0 68 128 109 149 (WSS:106) 19 (128-109) - - - Amplitude 128112 112 128112 112 - - - horizontal pixel counter 0 horizontal sync (HS) 1 horizontal clamp (HC) 31 start / stop programmable line length (programmable) newline (internal signal) start of video output (programmable) active video out (AVO) start / stop programmable vertical sync (VS), field 1 16 vertical sync (VS), field 2 line length/2 field 1 field 2 Fig. 2-16: Horizontal timing for line-locked mode 255 black level WSS SIgnal 174 Helper Burst (demodulated) 255 128 68 19 0 binary format signed format Fig. 2-17: PAL+ helper reference line output signal Micronas 21 VPC 323xD 2.11. Video Sync Processing Fig. 2-18 shows a block diagram of the front-end sync processing. To extract the sync information from the video signal, a linear phase lowpass filter eliminates all noise and video contents above 1 MHz. The sync is separated by a slicer; the sync phase is measured. A variable window can be selected to improve the noise immunity of the slicer. The phase comparator measures the falling edge of sync, as well as the integrated sync pulse. The sync phase error is filtered by a phase-locked loop that is computed by the FP. All timing in the front-end is derived from a counter that is part of this PLL, and it thus counts synchronously to the video signal. A separate hardware block measures the signal back porch and also allows gathering the maximum/minimum of the video signal. This information is processed by the FP and used for gain control and clamping. PRELIMINARY DATA SHEET For vertical sync separation, the sliced video signal is integrated. The FP uses the integrator value to derive vertical sync and field information. The information extracted by the video sync processing is multiplexed onto the hardware front sync signal (FSY) and is distributed to the rest of the video processing system. The format of the front sync signal is given in Fig. 2-19. Frequency and phase characteristics of the analog video signal are derived from PLL1. The results are fed to the scaler unit for data interpolation and orthogonalization and to the clock synthesizer for line-locked clock generation. Horizontal and vertical syncs are latched with the line-locked clock. PLL1 lowpass 1 MHz & syncslicer video input frontend timing clamp & signal meas. clamping, colorkey, FIFO_write clock synthesizer syncs clock H/V syncs horizontal sync separation phase comparator & lowpass counter front sync generator front sync skew vblank field vertical sync separation Sawtooth Parabola Calculation FIFO vertical serial data vertical E/W sawtooth Fig. 2-18: Sync separation block diagram F1 input analog video skew LSB skew not MSB used F V F0 reserved (not in scale) F0 F1 V: vertical sync 0 = off Parity 1 = on F: field # 0 = field 1 1 = field 2 FSY Fig. 2-19: Front sync format 22 Micronas PRELIMINARY DATA SHEET VPC 323xD field 1 CCIR 623 624 625 1 2 3 4 5 6 7 8 23 24 Front-Sync (FSY) Vertical Sync (VS) Interlace (INTLC) > 1clk field 2 CCIR 310 311 312 313 314 315 316 317 318 319 320 335 336 Vertical Sync (VS) Interlace (INTLC) >1 clk Active Video Output (AVO) helper ref line 23, 623 (internal signal) signal matches output video The following signals are identical for field1 / field2 helper lines 23-59, 275-310, 336-371, 587-623 (internal signal), signal matches output video Fig. 2-20: Vertical timing of VPC 323xD shown in reference to input video. Video output signals are delayed by 3-h for comb filter version (VPC 323xD). Micronas 23 VPC 323xD 2.12. Picture in Picture (PIP) Processing and Control 2.12.1. Configurations To support PIP and/or scan rate conversion (SRC) applications, the VPC 323xD provides several control signals for an external field memory IC. Fig. 2-21 demonstrates two applications with a single VPC 323xD. In these cases the VPCsingle writes the main picture or one of several inset picture(s) into the field memory. Only one of these pictures is displayed PRELIMINARY DATA SHEET live. These configurations are suitable for features such as turner scan, still picture, still in picture and simple scan rate conversion. Fig. 2-22 shows an enhanced configuration with two VPC 323xD's. In this case, one live and several still pictures are inserted into the main live video signal. The VPC pip processes the inset picture and writes the original or decimated picture into the field memory. The VPCmain delivers the main picture, combines it with the inset picture(s) from the field memory and stores the combined video signal into a second field memory for the SRC. YCrCb YCrCb/RGB CVBS YC rC b VPC 323xD (single) FFRSTW FFWE,FFIE LLC1 field memory FIFORRD FIFORD LLC2 LLC2 AVO VS RGB DDP 331x H/V Def. YCrCb YCrCb/RGB CVBS VPC 323xD (single) FFRSTW FFWE,FFIE LLC1 field memory YCrCb FFRE VS LLC1 LLC1 AVO VS Fig. 2-21: Typical configurations with single VPC 323xD YCrCb/RGB VPC 323xD (pip) field FFRSTW memory FFWE FFIE LLC1 FFRSTW* YCrCb (for PIP) YCrCb YCrCb FFRSTW FFRE FFOE CVBS (for PIP) LLC1 YCrCb FFWE FFIE VS LLC1 YCrCb/RGB CVBS (for main picture) VPC 323xD (main) field FIFORRD memory (for SRC) FIFORD LLC2 LLC2 AVO VS RGB DDP 331x H/V Def. * only used in the field-buffer-extension mode and the double-windows-extension mode Fig. 2-22: Enhanced configuration with two VPC 323xD 24 Micronas PRELIMINARY DATA SHEET VPC 323xD The inset pictures are displayed with or without a frame controlled by I2C. The fixed frame width is 4 pixels and 4 lines. Table 2-10: Inset picture size (without frame) in the predefined PIP modes size horizontal [pixel/line] 4:3 screen 13.5 MHz 1/2 1/3 1/4 1/6 332 220 164 112 16 MHz 392 260 196 132 16:9 screen 13.5 MHz 248 164 124 84 16 MHz 292 196 148 96 132 88 66 44 110 74 56 36 vertical [line/field] 625 line 525 line A summary of VPC modes is given in Table 2-9. Table 2-9: VPC 323xD modes for PIP applications Working mode pip Function - decimate the video signal for the inset pictures - write the inset pictures into the field memory - write the frame and background into the field memory - deliver the video signal for the main picture - read the inset pictures from the field memory and insert them into the main picture - write the resulting video signal into the field memory for the scan rate conversion (SRC) - decimate the video signal for the main or the inset picture(s) - write the inset pictures into the field memory - write the frame and background into the field memory - write the main picture part outside the inset pictures into the field memory - read the field memory (optional) main single 2.12.2. PIP Display Modes To minimize the programming effort, 15 predefined PIP modes are already implemented, including double windows, single and multi-PIP (Fig. 2-23 and 2-24). In addition an expert mode is available for advanced PIP applications. In this case the inset picture size, as well as the PIP window arrangements are fully programmable. Examples for the PIP mode programming are given in 5.2. 2.12.3. Predefined Inset Picture Size The predefined PIP display modes are based on four fixed inset picture sizes (see Table 2-10). The corresponding picture resizing is achieved by the integrated horizontal and vertical scaler of VPC 323xD, which must be programmed accordingly (see Table 2-11 to 2-13). Micronas 25 VPC 323xD PRELIMINARY DATA SHEET Table 2-11: Scaler Settings for predefined PIP modes at 13.5 MHz PIP size SCINC1 FP h'43 full 1/2 1/3 1/4 1/6 h'600 h'600 h'480 h'600 h'480 FFLIM FP h'42 h'2d0 h'168 h'f0 h'b4 h'78 h'168 4:3 SCPIP FP h'41 h'00 h'11 h'16 h'1a h'1f h'01 SCBRI FP h'52 h'010 h'110 h'210 h'210 h'310 h'110 SCINC1 FP h'43 h'800 h'400 h'600 h'400 h'600 h'600 16:9 FFLIM FP h'42 h'21c h'10e h'b4 h'87 h'5a h'168 SCPIP FP h'41 h'00 h'1a h'1b h'1b h'1f h'01 SCBRI FP h'52 h'010 h'210 h'210 h'310 h'310 h'110 double win h'600 Note: BR=16 in register SC-BRI!: Table 2-12: Scaler Settings for predefined PIP modes at 16 MHz PIP size SCINC1 FP h'43 full 1/2 1/3 1/4 1/6 h'510 h'510 h'798 h'510 h'798 FFLIM FP h'42 h'354 h'1aa h'11c h'd5 h'8e h'1aa 4:3 SCPIP FP h'41 h'00 h'11 h'15 h'1a h'1e h'01 SCBRI FP h'52 h'010 h'110 h'110 h'210 h'210 h'110 SCINC1 FP h'43 h'6c0 h'6c0 h'510 h'6c0 h'510 h'510 16:9 FFLIM FP h'42 h'27f h'140 h'd4 h'a0 h'6a h'1aa SCPIP FP h'41 h'00 h'11 h'16 h'1a h'1f h'01 SCBRI FP h'52 h'010 h'110 h'210 h'210 h'310 h'110 double win h'510 Note: BR=16 in register SC-BRI!: Table 2-13: Settings for NEWLIN, AVSTRT and AVSTOP PIP size NEWLIN I2C h'22 VPCsingle or VPCpip VPCmain 13.5 MHz AVSTRT I2C h'28 AVSTO P I2C h'29 NEWLIN I2C h'22 VPCsingle or VPCpip 16.0 MHz AVSTRT I2C h'28 AVSTO P I2C h'29 VPCmain full 1/2...1/6 h'86 h'194 h'86 h'86 h'86 h'86 h'86 h'86 h'356 h'356 h'356 h'a8 h'1de h'a8 h'a8 h'a8 h'a8 h'a8 h'a8 h'a8 h'3f0 h'3f0 h'3f0 double win h'86 Note: NEWLIN and AVSTRT must be > 47, if FIFOTYPE=0 or 1 26 Micronas PRELIMINARY DATA SHEET VPC 323xD . P1 P2 Mode 0 Mode 1 P1 PIP P2 P4 Mode 6 P3 Mode 2, 3, 4, 5 P1 P3 P2 P4 P1 P2 P3 Mode 7 Mode 8 P1 P3 P4 Mode 9 P2 P4 P6 P1 P4 P7 P2 P5 P8 P3 P6 P9 Mode 10 (4:3) Fig. 2-23: Predefined PIP Modes Micronas 27 VPC 323xD PRELIMINARY DATA SHEET P1 P5 P9 P2 P6 P10 P3 P7 P11 P4 P8 P12 P1 P2 P3 Mode 10 (16:9) Mode 11 (4:3) P1 P2 P3 P9 P10 P8 P4 Mode 12 P4 Mode 11 (16:9) P1 P2 Mode 13 Mode 14 P1 P2 P3 Fig. 2-24: Predefined PIP Modes (continued) 28 Micronas PRELIMINARY DATA SHEET VPC 323xD 2.12.5. Frame and Background Color Two programmable frame colors COLFR1 and COLFR2 are available to high-light a particular inset picture. Instead of displaying the main picture it is possible to fill the background with a programmable color COLBGD (set SHOWBGD=1 in the register PIPMODE), e. g. for multi PIP displays on the full screen (see mode 6 and 10). COLFR1, COLFR2 and COLBGD are 16 bits wide each. Therefore 65536 colors are programmable. 2.12.4. Acquisition and Display Window The acquisition window defines the picture area of the input active video to be displayed as a inset picture on the screen. The display window defines the display position of the inset picture(s) on the screen. The acquisition and display windows are controlled by I2C parameters HSTR, VSTR, NPIX and NLIN (see Fig. 2-25 and 2-26). They indicate the coordinate of the upper-left corner and the horizontal and vertical size of the active video area. In VPCpip or VPCsingle mode, these four parameters define the acquisition window in the decimated pixel grid, while in VPCmain mode they define the display window. 2.12.6. Vertical Shift of the Main Picture The VPCmain mode supports vertical up-shifting of the main picture (e. g. letterbox format) to enable bottom insets (see mode 11). The vertical shift is programmable by VOFFSET. HSTR VSTR 2.12.7. Free Running Display Mode NLIN In this mode a free running sync raster is generated to guarantee a stable display in critical cases like tuner scan. Therefore the LLC should be disabled (see Table 2-14). Acquisition Window NPIX Active Video 2.12.8. Frame and Field Display Mode In frame display mode, every field is written into the field memory. In the field display mode every second field is written into the field memory. This configuration is suitable for multi picture insets and freeze mode, since it avoids motion artifacts. On the other hand, the frame display mode guarantees maximum vertical and temporal resolution for animated insets. In the predefined mode the setting of frame/field mode is done automatically to achieve the best performance. Fig. 2-25: Definition of the acquisition window HSTR VSTR NLIN Display Window NPIX Active Video Fig. 2-26: Definition of the display window Micronas 29 VPC 323xD PRELIMINARY DATA SHEET Table 2-14: Settings for Free-Running Mode Control bit Function VPCsingle write PIP LLC_CLKC (bit[11] of FP h'6d) FLW (bit[15] of I2C h'28) VS_LOCK1) (bit[14] of I2C h'84) enable/disable LLC PLL enable/disable freerunning sync mode 1 1 write main pic. 0 0 0 0 0 0 VPCpip VPCmain predef. all other mode 6, 10 modes 1 1 1 0 or 12) 0 or 12) 0 or 12) synchronize PIP control 0 to input video/ free-running sync signals 1) VS_LOCK has to be enabled, before enable of FLW. 2) In case of "no input video" for VPCmain, it is recommended to enable the free running mode for stable PIP display. 2.12.9. External Field Memory The requirements of the external field memory are: - FIFO type access with reset - write mask function: The increasing of the write address pointer and the over writing of the data should be controlled separately. - output disable function: tri-state table outputs For PIP applications, VPC 323xD supports 4:1:1 or 4:2:2 chrominance format. Table 2-15 shows the typical memory size for a 13.5 and 16 MHz system clock application. Table 2-15: Word length and minimum size of the field memory Chrominance format 4:1:1 4:2:2 Word length [bit] 12 16 Memory size [word] 245376 245376 [bit] 2944512 3926016 RSTWR (reset write/read) resets the internal write/ read address pointer to zero. WE (write enable) is used to enable or disable incrementing of the internal write address pointer. IE (input enable) is used to enable writing data from the field memory input pins into the memory core, or to disable writing and thereby preserving the previous content of the memory (write mask function). RE (read enable) is used to enable or disable incrementing the internal read address pointer. OE (output enable) is used to enable or disable data output to the output pins. As serial write and serial read clock (SWCK and SRCK, respectively) of the field memory the line locked clocks LLC1 and/or LLC2 are used. The following 5 signals are generated by VPC 323xD to control the external field memory: 30 Micronas PRELIMINARY DATA SHEET VPC 323xD 2.12.10. Field-Buffer-Extension Mode The field-buffer-extension mode provides a joint lines free display of the inset picture for the single PIP modes. In this mode, two frames (four fields) of the inset picture are stored in the external field memory. The write/read controlling detects timing conflicts causing joint lines artifacts and suppresses these conflicts automatically. Table 2-16: Function of the I2C bits TWOFB and FRAMOD FBEXT x x 0 1 1 TWOFB 0 0 1 1 1 FRAMOD 0 1 x 0 1 Function use one field buffer, write only one input field of a frame into it use one field buffer, write both input fields of a frame into it use two field buffers, write two input fields of a frame alternate into them use two field buffers, write input fields of a frame alternate into them, update the PIP frame while writing the inset picture use four field buffers, write input fields of two frame alternate into them, update the PIP frame while writing the inset picture Therefore, the output pin FFRSTW of VPCpip has to be connected to the input pin RSTWPIP (see Fig. 2-22) For the predefined PIP modes 2...5, the field-bufferextension mode is enabled by FBEXT=1, in expert mode by FBEXT=1, TWOFB=1 and FRAMOD=1. The function of the I2C bits TWOFB and FRAMOD is shown in Table 2-24 2.12.11. Double-Windows-Extension Mode The double-windows-extension mode provides a joint fields free display of the second picture in Double-Window mode. The write/read controlling detects timing conflicts causing joint fields and suppresses these conflicts automatically by delaying the read control signals. The output pin FFRSTW of VPCpip should be connected to the input pin RSTWPIP (see Fig. 2-22) Micronas 31 VPC 323xD 3. Serial Interface 3.1. I2C-Bus Interface Communication between the VPC and the external controller is done via I2C-bus. The VPC has an I2C-bus slave interface and uses I2C clock synchronization to slow down the interface if required. The I2C-bus interface uses one level of subaddress: one I2C-bus address is used to address the IC and a subaddress selects one of the internal registers. For multi VPC 323xD applications the following three I2C-bus chip addresses are selectable via I2CSEL pin: A6 1 1 1 A5 0 0 0 A4 0 0 0 A3 0 0 0 A2 1 1 1 A1 1 1 0 A0 R/W I2CSEL 1 0 0 1/0 1/0 1/0 VSUP VRT GND PRELIMINARY DATA SHEET The registers of the VPC have 8 or 16-bit data size; 16-bit registers are accessed by reading/writing two 8-bit data words. Figure 3-1 shows I2C-bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the chip address with read command set. 3.2. Control and Status Registers Table 3-1 gives definitions of the VPC control and status registers. The number of bits indicated for each register in the table is the number of bits implemented in hardware, i.e. a 9-bit register must always be accessed using two data bytes but the 7 MSB will be `don't care' on write operations and `0' on read operations. Write registers that can be read back are indicated in Table 3-1. S 1000 111 W Ack FPWR Ack send FP-addressbyte high Ack send FP-addressbyte low Ack P I2C write access to FP S 1000 111 W Ack FPDAT Ack send databyte high Ack send databyte low Ack P S 1000 111 W Ack FPRD Ack send FP-addressbyte high Ack send FP-addressbyte low Ack P I2C read access to FP S 1000 111 W Ack FPDAT Ack S 1000 111 R Ack receive databyte high receive databyte low Ack Nak P S 1000 111 W Ack 0111 1100 Ack 1 or 2 byte Data P I2C write access subaddress 7c I2C read access subaddress 7c S 1000 111 W Ack 0111 1100 Ack S 1000 111 R Ack high byte Data Ack low byte Data Nak P SDA 1 0 S P SCL W R Ack Nak S P = = = = = = 0 1 0 1 Start Stop Fig. 3-1: I2C-bus protocols 32 Micronas PRELIMINARY DATA SHEET VPC 323xD The register modes given in Table 3-1 are - w: - w/r: - r: - v: write only register write/read data register read data from VPC register is latched with vertical sync A hardware reset initializes all control registers to 0. The automatic chip initialization loads a selected set of registers with the default values given in Table 3-1. The mnemonics used in the Micronas VPC demo software are given in the last column. Micronas 33 VPC 323xD Table 3-1: Control and status registers I2C Subaddress Number of bits Mode Function PRELIMINARY DATA SHEET Default Name FP Interface h'35 8 r FP status bit [0] bit [1] bit [2] bit[8:0] bit[11:9] bit[8:0] bit[11:9] bit[11:0] - write request read request busy 9-bit FP read address reserved, set to zero 9-bit FP write address reserved, set to zero FP data register, reading/writing to this register will autoincrement the FP read/ write address. Only 16 bit of data are transferred per I2C telegram. Black Line Detector h'12 16 w/r read only register, do not write to this register! After reading, LOWLIN and UPLIN are reset to 127 to start a new measurement. bit[6:0] number of lower black lines bit[7] always 0 bit[14:8] number of upper black lines bit[15] 0/1 normal/black picture Pin Circuits h'1F 16 w/r SYNC PIN CONTROL: bit[2:0] 0 reserved (set to 0) bit[3] 0/1 push-pull/tri-state for AVO Pin bit[4] 0/1 push-pull/tri-state for other video SYNC Pins bit[5] 0 reserved (set to 0) CLOCK/FIFO PIN CONTROL: bit[6] 0/1 push-pull/tri-state for LLC1 bit[7] 0/1 push-pull/tri-state for LLC2 bit[8] 0/1 push-pull/tri-state for CLK20 bit[9] 0/1 push-pull/tri-state for FIFO control pins LUMA/CHROMA DATA PIN (LB[7:0], CB[7:0]) CONTROL: bit[10] 0/1 tri-state/push-pull for Chroma Data pins bit[11] 0/1 tri-state/push-pull for Luma Data pins bit[15:12] reserved (set to 0) SYNC GENERATOR CONTROL: bit[1:0] 00 AVO and active Y/C data at same time 01 AVO precedes Y/C data one clock cycle 10 AVO precedes Y/C data two clock cycles 11 AVO precedes Y/C data three clock cycles bit[2] 0/1 positive/negative polarity for HS signal bit[3] 0/1 positive/negative polarity for HC signal bit[4] 0/1 positive/negative polarity for AVO signal bit[5] 0/1 positive/negative polarity for VS signal bit[6] 0 reserved (set to 0) bit[7] 0/1 positive/negative polarity for INTLC signal TRPAD 0 0 0 0 0 0 0 0 0 0 0 0 AVODIS SNCDIS - BLKLIN - - - FPRD FPWR FPDAT FPSTA h'36 h'37 h'38 16 16 16 w w w/r LOWLIN UPLIN BLKPIC LLC1DIS LLC2DIS CLK20DIS FFSNCDIS CDIS YDIS h'20 8 w/r SYNCMODE AVOPRE 0 0 0 0 0 0 HSINV HCINV AVOINV VSINV INTLCINV 34 Micronas PRELIMINARY DATA SHEET VPC 323xD Table 3-1: Control and status registers I2C Subaddress Number of bits Mode Function Default Name h'23 16 w/r OUTPUT STRENGTH: bit[3:0] 0..15 output pin strength (0 = strong, 15 = weak) bit[9:4] address of output pin 32 FIFO control pins FFIE, FFOE, FFWR, FFRE and FFRSTWR 33 SYNC pins AVO, HS, HC, INTERLACE,VS bit[10] 0/1 read/write output strength bit[15:11] reserved (set to 0) V-SYNC DELAY CONTROL: bit[7:0] VS delay (8 LLC clock cycles per LSB) 656 Interface 0 0 OUTSTR PADSTR PADADD 0 0 0 PADWR VSDEL VSDEL h'30 8 w/r h'24 8 w/r 656 OUTPUT INTERFACE bit [0] 1 disable hor. & vert. blanking of invalid data in 656 mode bit [1] 0 use vertical window as VFLAG 1 use vsync as VFLAG bit [2] enable suppression of 656-headers during invalid video lines bit [3] enable ITU-656 output format bit [4] 0/1 LLC1/LLC2 used as reference clock bit [5] 0/1 output mode: DIGIT 3000 / LLC Sync Generator OUT656 0 DBLNK 0 VSMODE 0 HSUP 0 656enable 0 DBLCLK 1 OMODE h'21 16 w/r LINE LENGTH: bit[10:0] bit[15:11] h'26 16 w/r HC START: bit[10:0] LINE LENGTH register In LLC mode, this register defines the cycle of the sync counter which generates the SYNC pulses. In LLC mode, the synccounter counts from 0 to LINE LENGTH, so this register has to be set to "number of pixels per line -1". In DIGIT3000 mode, LINE LENGTH has to be set to 1295 for correct adjustment of vertical signals. reserved (set to 0) HC START defines the beginning of the HC signal in respect to the value of the sync counter. reserved (set to 0) select pos./neg. polarity of HSYA/VSYA dis-/enable Front-End horizontal and vertical sync outputs HSYA/VSYA HC STOP defines the end of the HC signal in respect to the value of the sync counter. reserved (set to 0) 1295 LINLEN 50 HCSTRT bit[13:11] bit[14] 0/1 bit[15] 0/1 h'27 16 w/r bit[10:0] bit[15:11] 0 0 800 HVSYAPOL HVSYA HCSTOP Micronas 35 VPC 323xD Table 3-1: Control and status registers I2C Subaddress Number of bits Mode Function PRELIMINARY DATA SHEET Default Name h'28 16 w/r AVO START: bit[10:0] bit[11] bit[12] bit[13] bit[14] bit[15] h'29 16 w/r 0/1 0/1 0/1 0/1 AVO START defines the beginning of the AVO signal in respect to the value of the sync counter. reserved (set to 0) dis-/enable suppression of AVO during VBI and invalid video lines vertical standard for flywheel (312/262 lines) used if FLW is set disable interlace for flywheel enable vertical free run mode (flywheel) AVO STOP defines the end of the AVO signal in respect to the value of the sync counter. reserved for test picture generation (set to 0 in normal operation) disable/enable test pattern generator luma output mode: Y = ramp (240 ... 17) Y = 16 Y = 90 Y = 240 chroma output: 422/411 mode chroma output: pseudo color bar/zero if LMODE = 0 NEWLINE defines the readout start of the next line in respect to the value of the sync counter. The value of this register must be greater than 34 for correct operation and should be identical to AVOSTART (recommended). In case of 1H-bypass mode for scaler block, NEWLINE has no function. reserved (set to 0) 60 AVSTRT 0 0 AVOGATE FLWSTD DIS_INTL FLW AVSTOP 0 0 AVO STOP: bit[10:0] bit[15:11] bit[11] 0/1 bit[13:12] 00 01 10 11 bit[14] 0/1 bit[15] 0/1 h'22 16 w/r NEWLINE: bit[10:0] 0 0 COLBAREN LMODE 0 0 M411 CMODE 50 NEWLIN bit[15:11] 36 Micronas PRELIMINARY DATA SHEET VPC 323xD Table 3-1: Control and status registers I2C Subaddress Number of bits Mode Function Default Name PIP Control h'84 16 w/r VPC MODE: bit[0] 0/1 bit[1] 0/1 bit[2] 0/1 bit[3] 0/1 bit[4] 0/1 bit[5] 0/1 0 VPCMODE dis-/enable field memory control for PIP double/single VPC application select VPCpip/VPC main mode 4:3/16:9 screen 13.5/16 MHz output pixel rate vertical PIP window size is based on a 625/525 line video bit[7:6] field memory type 00 reserved 01 PHILIPS SAA 4955TJ 10 reserved 11 other (OKI MSM5412222, ...) bit[11:8] are evaluated only, if bit[7:6]=11 bit[8] 0/1 delay the video output compared to WE for 0/1 LLC1 clock, if DBLCLK=0 0/1 LLC2 clock, if DBLCLK=1 bit[9] 0/1 pos/neg polarity for WE and RE signals bit[10] 0/1 pos/neg polarity for IE and OE signals bit[11] 0/1 pos/neg polarity for RSTWR signal bit[12] reserved (set to 0) bit[13] 0/1 vertical PIP position synchronized by input video/vertical sync in case of no video input, FLW=0 and LLC PLL disabled. For VPC main combined with a feature-box without read/write mask only! bit[14] 0/1 vertical PIP position synchronized by input video/free running sync raster FLW bit[15] reserved (set to 0) This register is updated when the PIPOPER register is written. ENA_PIP SINGVPC MAINVPC F16TO9 F16MHZ W525 FIFOTYPE VIDEODEL WEREINV IEOEINV RSTWRINV AV_LOCK VS_LOCK Micronas 37 VPC 323xD Table 3-1: Control and status registers I2C Subaddress Number of bits Mode Function PRELIMINARY DATA SHEET Default Name h'85 16 w/r 0 PIP MODE: bit[3:0] 0 - 14 select predefined PIP mode 15 select expert mode bit[5:4] are used for expert mode only bit[4] 0/1 write one/both input field(s) of a frame into the field buffer in case TWOFB=0 bit[5] 0/1 use one/two field buffer(s) Note: please see 2.12.10 for detailed description of FRAMOD and TWOFB in field-buffer-extension mode bit[6] 0/1 show video/the background color in the picture bit[13:7] are used for VPCmain only bit[7] 0/1 dis-/enable the vertical up-shifting of the main picture bit[13:8] 0...62 number of lines for vertical up-shift bit[14] 0/1 dis-/enable the field-buffer-extension mode, only used for VPCpip and VPCmain in single PIP Modes bif[15] 0/1 dis-/enable the double-window-extension mode, only used for VPCmain in predefined mode 1 This register is updated when the PIPOPER register is written. PIPMODE MODSEL FRAMOD TWOFB SHOWBGD VSHIFT VOFFSET FBEXT DWEXT 38 Micronas PRELIMINARY DATA SHEET VPC 323xD Table 3-1: Control and status registers I2C Subaddress Number of bits Mode Function Default Name h'83 8 w/r PIP OPERATION: For VPCpip or VPCsingle: bit[1:0] the number of the inset picture to be accessed in the x-direction bit[3:2] the number of the inset picture to be accessed in the y-direction bit[6:4] 000 start to write the inset picture with a frame 001 stop writing 010 fill the frame with the color COLFR1 011 fill the frame with the color COLFR2 100 fill the inset picture with a frame using the color COLBGD 101 fill the inset picture w/o a frame using the color COLBGD 110 start to write the inset picture w/o a frame 111 write the main picture (VPCsingleonly) 0 PIPOPER NSPX NSPY WRPIC WRSTOP WRFRCOL1 WRFRCOL2 WRBGD WRBGDNF WRPICNF WRMAIN For VPCmain: bit[3:0] bit[6:4] 000 001 010 011 100 101 other bit[7] 0/1 reserved set to 0 start to display PIP stop to display PIP enable still main picture1) disable still main picture1) enable still PIP1) disable still PIP1) reserved set to 0 processed/new command flag, normally write 1. After the new PIP setting takes effect, this bit is set to 0 to indicate operation complete. DISSTART DISSTOP STMAINON STMAINOFF STPIPON STPIPOFF NEWCMD 1) This Mode is available only in combination with a FIFO type field memory (see Section 2.12.9.) for scan rate conversion. 0 COLBGD h'80 16 w/r BACKGROUND COLOR: in binary offset bit[[4:0] bit b7 to b3 of the chrominance component C R bit[9:5] bit b7 to b3 of the chrominance component C B bit[15:10] bit b7 to b2 of the luminance component Y (all other bits of YCBCR are set to 0) This register is updated when the PIPOPER register is written. h'81 16 w/r FRAME COLOR 1: in binary offset Only used for VPCpip or VPCsingle: bit[[4:0] bit b7 to b3 of the chrominance component C R bit[9:5] bit b7 to b3 of the chrominance component C B bit[15:10] bit b7 to b2 of the luminance component Y (all other bits of YCBCR are set to 0) This register is updated when the PIPOPER register is written. h'3e0 COLFR1 Micronas 39 VPC 323xD Table 3-1: Control and status registers I2C Subaddress Number of bits Mode Function PRELIMINARY DATA SHEET Default Name h'82 16 w/r FRAME COLOR 2: in binary offset only used for VPCpip or VPCsingle: bit[[4:0] bit b7 to b3 of the chrominance component CR bit[9:5] bit b7 to b3 of the chrominance component CB bit[15:10] bit b7 to b2 of the luminance component Y (all other bits of YCBCR are set to 0) This register is updated when the PIPOPER register is written. h'501f COLFR2 h'86 16 w/r LINE OFFSET: Only used for VPCpip or VPCsingle: bit[8:0] line offset of the upper-left corner of the inset picture with NSPX=0 and NSPY=0 in the display window bit[9] 0/1 use the internal default/external setting via bit[8:0] bit[15:10] reserved (set to 0) This register is updated when the PIPOPER register is written. 0 LINOFFS h'89 16 w/r PIXEL OFFSET: Only used for VPCpip or VPCsingle: bit[7:0] quarter of the pixel offset of the upper-left corner of the inset picture with NSPX=0 and NSPY=0 in the display window bit[8] 0/1 use the internal default/external setting via bit[7:0] bit[15:9] reserved (set to 0) This register is updated when the PIPOPER register is written. 0 PIXOFFS 40 Micronas PRELIMINARY DATA SHEET VPC 323xD Table 3-1: Control and status registers I2C Subaddress Number of bits Mode Function Default Name h'87 16 w/r VERTICAL START: bit[8:0] For VPCpip and VPCsingle: vertical start of the active video segment to be used as a inset picture For VPCmain : vertical start of the inset picture(s) in the main picture Exception: bit[8:0] 0...3 For VPCmain in predefined mode 1 and DWEXT=1: length (in lines) of the FIFO read-write conflict interval 0 length = 1 1 length = 1 2 length = 2 3 length = 3 =1 for PHILIPS SAA 4955TJ, OKI MSM541222,... bit[9] 0/1 use the internal default/external setting via bit[8:0] 0 VSTR Only used for predefined mode 1 and DWEXT=1: bit[11:10] start position (in line number) of the the FIFO read-write conflict interval 00 PHILIPS SAA 4955TJ 01 OKI MSM541222,... bit[15:12] defines max. drift (in LLC1 clocks) between the rstwr impulses of VPCpip and VPCmain, where the double-windowextension mode is active. h'8a 16 w/r 0 VSTR_JF 0 DIFLIM HORIZONTAL START: 0 bit[7:0] For VPCpip and VPCsingle: horizontal start of the active video segment to be used as a inset picture For VPCmain: horizontal start of the inset picture(s) in the main picture In both cases HSTR is given by the number of 4-pixel-groups. bit[8] 0/1 use the internal default/external setting via bit[7:0] bit[15:9] reserved (set to 0) NUMBER OF LINES: Only used in the expert modes: bit[8:0] For VPCpip and VPCsingle: number of lines of the active video segment to be used as a inset picture For VPCmain: number of lines of the inset picture(s) bit[15:9] reserved (set to 0) This register is updated when the PIPOPER register is written. 0 HSTR h'88 16 w/r NLIN Micronas 41 VPC 323xD Table 3-1: Control and status registers I2C Subaddress Number of bits Mode Function PRELIMINARY DATA SHEET Default Name h'8b 8 w/r NUMBER OF PIXEL PER LINE: Only used in the expert modes: bit[7:0] For VPCpip and VPCsingle: quarter of the number of pixels per line in the active video segment to be used as a inset picture For VPCmain: quarter of the number of pixels per line of the inset picture(s) This register is updated when the PIPOPER register is written. 0 NPIX h'8c 16 w/r NUMBER OF PIXEL PER LINE IN THE FIELD BUFFER(S): bit[7:0] bit[8] 0/1 quarter of the number of allocated pixels per line in the field buffer(s) use the internal default/external setting via bit[7:0] (must be set in the expert mode, optional in the predefined modes) reserved (set to 0) 0 NPFB bit[15:9] This register is updated when the PIPOPER register is written. h'8dh'8f reserved, don't write CIP Control h'90 16 w/r SATURATION OF THE RGB/YCrCb COMPONENT INPUT: bit[5:0] saturation Cb( 0..63 ) bit[11:6] saturation Cr( 0..63 ) bit[15:12] reserved (set to 0) TINT CONTROL OF THE RGB/YUV COMPONENT INPUT: bit[5:0] tint ( -20..+20 in degrees ) bit[7:6] reserved (set to 0) BRIGHTNESS OF THE RGB/YUV COMPONENT INPUT: bit[7:0] brightness ( -128..+127 ) CONTRAST OF THE RGB/YUV COMPONENT INPUT: bit[13:8] contrast ( 0..63 ) bit[15:14] reserved (set to 0) SOFTMIXER CONTROL: bit[0] 0/1 rgb/main video delay (0:normal 1:dynamic) bit[1] 0/1 linear (0)/nonlinear(1) mixer select bit[7:4] fastblank gain (-7 .. +7) bit[3:2] reserved (set to 0) SOFTMIXER CONTROL: bit[5:0] fastblank offset correction (0..63 ) ( fb -> fb-FBOFFS ) bit[7:6] fastblank mode: x0 force rgb to cip out (equ. fb=0) 01 normal mode (fb active) 11 force main yuv to cip out (equ. fb=64) 23 29 CIPSAT SATCb SATCr h'91 8 w/r 0 CIPTNT CIPBRCT CIPBR CIPCT CIPMIX1 RGBDLY SELLIN FBGAIN CIPMIX2 FBOFFS FBMODE h'92 16 w/r 68 27 h'94 8 w/r 0 0 -1 h'95 8 w/r 32 11 42 Micronas PRELIMINARY DATA SHEET VPC 323xD Table 3-1: Control and status registers I2C Subaddress Number of bits Mode Function Default Name h'96 8 w/r ADC RANGE : bit[0] reserved (set to 0) bit[1] 0/1 0/+3dB extended ADC range INPUT PORT SELECT : bit[2] 0/1 1/2 input port select SOFTMIXER CONTROL: bit[5] 0/1 clamp fb to a programable value (0:normal 1: fb=31-FBOFFS ) bit[6] 0/1 bypass chroma 444->422 decimation filter RGB/YUV SELECT: bit[7] 0/1 rgb/yuv input select bit[4:3] reserved (set to 0) FB MONITOR: bit[0] 0/1 bit[1] 0/1 bit[2] 0/1 bit[3] 0/1 set by fb high, reset by reg. read and fb low set by fb falling edge, reset by reg. read set by fb rising edge, reset by reg. read fb status at register read CIPCNTL 0 0 0 1 0 XAR RGBSEL FBCLP CIPCFBY YUV CIPMON FBHIGH FBFALL FBRISE FBSTAT h'97 8 r - - - - - CLIP DETECTOR: bit[4] 0/1 rgb/yuv input clip detect, reset by read Hardware ID h'9f 16 r Hardware version number bit[7:0] 0/255 hardware id 1=A, 2=B aso. bit[11:8] 0/3 product code 0 VPC32x0D 1 VPC32x1D 2 VPC32x2D 3 VPC32x3D bit[15:12] 0/15 product code 3 VPC323xD 100Hz version 4 VPC324xD 50Hz version CLIPD read only Micronas 43 VPC 323xD Table 3-2: Control Registers of the Fast Processor PRELIMINARY DATA SHEET - default values are initialized at reset - * indicates: register is initialized according to the current standard when SDT register is changed. FP Subaddress Function Default Name Standard Selection h'20 Standard select: bit[2:0] standard 0 PAL B,G,H,I 1 NTSC M 2 SECAM 3 NTSC44 4 PAL M 5 PAL N 6 PAL 60 7 NTSC COMB 0/1 0 (50 Hz) (60 Hz) (50 Hz) (60 Hz) (60 Hz) (50 Hz) (60 Hz) (60 Hz) 4.433618 3.579545 4.286 4.433618 3.575611 3.582056 4.433618 3.579545 0 PAL NTSC SECAM NTSC44 PALM PALN PAL60 NTSCC SDTMOD SDT bit[3] MOD standard modifier PAL modified to simple PAL NTSC modified to compensated NTSC SECAM modified to monochrome 625 NTSCC modified to monochrome 525 PAL+ mode off/on 4-H COMB mode S-VHS mode: The S-VHS/COMB bits allow the following modes: composite input signal comb filter active S-VHS input signal CVBS mode (composite input signal, no luma notch) bit[4] bit[5] bit[6] 0/1 0/1 0/1 00 01 10 11 0 0 0 PALPLUS COMB SVHS Option bits allow to suppress parts of the initialization; this can be used for color standard search: bit[7] bit[8] bit[9] bit[10] bit[11] no hpll setup no vertical setup no acc setup 4-H comb filter setup only status bit, normally write 0. After the FP has switched to a new standard, this bit is set to 1 to indicate operation complete. Standard is automatically initialized when the insel register is written. 0 SDTOPT 44 Micronas PRELIMINARY DATA SHEET VPC 323xD FP Subaddress Function Default Name h'148 Enable automatic standard recognition bit[0] 0/1 PAL B,G,H,I (50 Hz) 4.433618 bit[1] 0/1 NTSC M (60 Hz) 3.579545 bit[2] 0/1 SECAM (50 Hz) 4.286 bit[3] 0/1 NTSC44 (60 Hz) 4.433618 bit[4] 0/1 PAL M (60 Hz) 3.575611 bit[5] 0/1 PAL N (50 Hz) 3.582056 bit[6] 0/1 PAL 60 (60 Hz) 4.433618 bit[10:7] reserved set to 0 bit[11] 1 reset status information bit `switch' in register `asr_status' (cleared automatically) 0: disable recognition; 1: enable recognition Note: For correct operation don't change FP reg. 20h and 21h, while ASR is enabled! 0 ASR_ENABLE h'14e Status of bit[0] bit[1] bit[2] bit[3] bit[4] bit[5] automatic standard recognition 1 error of the vertical standard (neither 50 nor 60 Hz) 1 detected standard is disabled 1 search active 1 search terminated, but failed 1 no color found 1 standard has been switched (since last reset of this flag with bit[11] of asr_enable) 00000 all ok 00001 search not started, because vwin error detected 0 ASR_STATUS VWINERR DISABLED BUSY FAILED NOCOLOR SWITCH bit[4:0] (no input or SECAM L) 00010 search not started, because detected vert. standard 0x1x0 01x00 01x10 10100 not enabled search started and still active search failed (found standard not correct) search failed, (detected color standard not enabled) no color found (monochrome input or switch betw. CVBS/SVHS necessary) Micronas 45 VPC 323xD PRELIMINARY DATA SHEET FP Subaddress Function Default Name h'21 Input select: bit[1:0] 00 01 10 11 bit[2] 0/1 bit[4:3] 00 01 10 11 bit[6:5] 00 01 10 11 0/1 0/1 00 01 10 11 bit[11] writing to this register will also initialize the standard luma selector VIN3 VIN2 VIN1 VIN4 chroma selector VIN1/CIN IF compensation off 6 dB/Okt 12 dB/Oct 10 dB/MHz only for SECAM chroma bandwidth selector narrow normal broad wide adaptive/fixed SECAM notch filter enable luma lowpass filter hpll speed no change terrestrial vcr mixed status bit, write 0, this bit is set to 1 to indicate operation complete. 0 INSEL VIS 1 0 CIS IFC 2 CBW bit[7] bit[8] bit[10:9] 0 0 3 FNTCH LOWP HPLLMD h'22 picture start position: This register sets the start point of active video and can be used e.g. for panning. The setting is updated when `sdt' register is updated or when the scaler mode register `scmode' is written. luma/chroma delay adjust. bit[5:0] reserved, set to zero bit[11:6] luma delay in clocks, allowed range is +1 ... -7 The setting is updated when `sdt' register is updated. helper delay register (PAL+ mode only) bit[11:0] delay adjust for helper lines adjustable from -96...96, 1 step corresponds to 1/32 clock component input to main video input delay matching bit[5:0] reserved, set to zero bit[11:6] delay adjust cip/main 0...18 clocks, 9=matched The setting is updated when `sdt' register is updated. VGA mode select, pull-in range is limited to 2% bit[1:0] 0 31.5 kHz 1 35.2 kHz 2 37.9 kHz 3 reserved is set to 0 by FP if VGA = 0 bit[10] 0/1 disable/enable VGA mode bit[11] status bit, write 0, this bit is set to 1 to indicate operation complete. 0 SFIF h'23 0 LDLY h'29 0 HLP_DLY h'27 9 CIP_MATCH VGA_C h'2f 0 VGAMODE 0 VGA 46 Micronas PRELIMINARY DATA SHEET VPC 323xD FP Subaddress Function Default Name Comb Filter h'28 comb filter control register bit[1:0] notch filter select 00 flat frequency characteristic 01 min. peaked 10 med. peaked 11 max. peaked bit[3:2] diagonal dot reduction 00 min. reduction ... 11 max. reduction bit[4:5] horizontal difference gain 00 min. gain ... 11 max. gain bit[7:6] vertical difference gain 00 max. gain ... 11 min. gain bit[11:8] vertical peaking gain 0 no vertical peaking... 15 max. vertical peaking comb filter test register bit[1:0] reserved, set ot 0 bit[2] 0/1 disable/enable vertical peaking DC rejection filter bit[3] 0/1 disable/enable vertical peaking coring bit[11:4] reserved, set to 0 Color Processing h'30 Saturation control bit[11:0] 0...4094 4095 bit[10:0] 0...2047 2070 (2070 corresponds to 100% saturation) reserved CR-attenuation or PAL+ Helper gain adjust (1591 corresponds to 100% helper gain 2047 corresponds to 100% CR gain) select Helper gain (CR-attenuation disabled) select CR-attenuation 1591 CR_ATT ACC_SAT h'e7 3 COMB_UC NOSEL 1 2 3 0 DDR HDG VDG VPK CMB_TST h'55 0 0 DCR COR h'17a bit[11] h'17d h'39 h'3a h'16c 0 1 0 1280 25 5 0 CR_ATT_ENA ACCH KILVL KILHY HLPDIS ACC multiplier value for PAL+ Helper Signal b[10:0] eeemmmmmmmm m * 2-e bit[10:0] 0..2047 amplitude killer level (0:killer disabled) amplitude killer hysteresis automatic helper disable for nonstandard signals bit[11:0] 0 automatic function disabled bit[1:0] 01 enable bit[11:2] 1..50 number of fields to switch on helper signal NTSC tint angle, 512 = /4 h'dc 0 TINT Micronas 47 VPC 323xD PRELIMINARY DATA SHEET FP Subaddress Function Default Name DVCO h'f8 h'f9 crystal oscillator center frequency adjust, -2048 ... 2047 crystal oscillator center frequency adjustment value for line-lock mode, true adjust value is DVCO - ADJUST. For factory crystal alignment, using standard video signal: disable autolock mode, set DVCO = 0, set lock mode, read crystal offset from ADJUST register and use negative value for initial center frequency adjustment via DVCO. crystal oscillator line-locked mode, lock command/status write: 100 enable lock 0 disable lock read: 0 unlocked >2047 locked crystal oscillator line-locked mode, autolock feature. If autolock is enabled, crystal oscillator locking is started automatically. bit[11:0] threshold, 0:autolock off -720 read only DVCO ADJUST h'f7 0 XLCK h'b5 400 AUTOLCK 48 Micronas PRELIMINARY DATA SHEET VPC 323xD FP Subaddress Function Default Name FP Status Register h'12 general purpose control bits bit[2:0] reserved, do not change bit[3] vertical standard force bit[8:4] reserved, do not change bit[9] disable flywheel interlace bit[11:10] reserved, do not change to enable vertical free run mode set vfrc to 1 and dflw to 0 standard recognition status bit[0] 1 vertical lock bit[1] 1 horizontally locked bit[2] 1 no signal detected bit[3] 1 color amplitude killer active bit[4] 1 disable amplitude killer bit[5] 1 color ident killer active bit[6] 1 disable ident killer bit[7] 1 interlace detected bit[8] 1 no vertical sync detection bit[9] 1 spurious vertical sync detection bit[12:10] reserved input noise level, available only for VPC 323xC number of lines per field, P/S: 312, N: 262 vertical field counter, incremented per field measured sync amplitude value, nominal: 768 (PAL), 732 (NTSC) measured burst amplitude firmware version number bit[7:0] internal revision number bit[11:8] firmware release hardware id see I2C register h'9f status of macrovision detection bit[0] AGC pulse detected bit[1] pseudo sync detected 0 1 VFRC DFLW h'13 - ASR h'14 h'cb h'15 h'74 h'36 h'f0 read only read only read only read only read only read only NOISE NLPF VCNT SAMPL BAMPL - h'170 read only MCV_STATUS Micronas 49 VPC 323xD PRELIMINARY DATA SHEET FP Subaddress Function Default Name Scaler Control Register h'40 scaler mode register bit[1:0] scaler mode 0 linear scaling mode 1 nonlinear scaling mode, 'panorama' 2 nonlinear scaling mode, 'waterglass' 3 reserved bit[2] reserved, set to 0 bit[3] color mode select 0/1 4:2:2 mode / 4:1:1 mode bit[4] scaler bypass bit[5] reserved, set to 0 bit[6] luma output format 0 ITU-R luma output format (16-240) 1 CVBS output format bit[7] chroma output format 0/1 ITU-R (offset binary) / signed bit[10:8] reserved, set to 0 bit[11] 0 scaler update command, when the registers are updated the bit is set to 1 pip control register bit[1:0] horizontal downsampling 0 no downsampling 1 downsampling by 2 2 downsampling by 4 3 downsampling by 8 bit[3:2] vertical compression for PIP 0 compression by 2 1 compression by 3 2 compression by 4 3 compression by 6 bit[4] vertical filter enable bit[5] interlace offset for vertical filter (NTSC mode only) 0 start in line 283 of 2nd field (ITUR 656 spec) 1 start in line 282 of 2nd field (NTSC spec) this register is updated when the scaler mode register is written active video length for 1H-FIFO bit[11:0] length in pixels D3000 mode (1296/h)1080 LLC mode (864/h)720 this register is updated when the scaler mode register is written scaler1 coefficient: This scaler compresses the signal. For compression by a factor c, the value c*1024 is required. bit[11:0] allowed values from 1024... 4095 This register is updated when the scaler mode register is written. scaler2 coefficient: This scaler expands the signal. For expansion by a factor c, the value 1/c*1024 is required. bit[11:0] allowed values from 256..1024 This register is updated when the scaler mode register is written. scaler1/2 nonlinear scaling coefficient This register is updated when the scaler mode register is written. 0 SCMODE PANO S411 BYE YOF COF h'41 0 SCPIP DOWNSAMP PIPSIZE PIPE INTERLACE_OFF h'42 1080 FFLIM h'43 1024 SCINC1 h'44 1024 SCINC2 h'45 0 SCINC 50 Micronas PRELIMINARY DATA SHEET VPC 323xD FP Subaddress Function Default Name h'47 - h'4b h'4c - h'50 h'52 scaler1 window controls, see table 5 12-bit registers for control of the nonlinear scaling This register is updated when the scaler mode register is written. scaler2 window controls, see table 5 12-bit registers for control of the nonlinear scaling This register is updated when the scaler mode register is written. brightness register bit[7:0] luma brightness -128...127 ITU-R output format: 16 CVBS output format: -4 bit[9:8] horizontal lowpass filter for Y/C 0 bypass 1 filter 1 2 filter 2 3 filter 3 bit[10] horizontal lowpass filter for highresolution chroma 0/1 bypass/filter enabled bit[11] 0/1 dis-/enable luma limited to 16 this register is updated when the scaler mode register is written contrast register bit[5:0] luma contrast 0..63 ITU-R output format: 48 bit[7:6] horizontal peaking filter 0 narrow 1 med 2 broad bit[10:8] peaking gain 0 no peaking... 7 max. peaking bit[11] peaking filter coring enable 0/1 bypass/coring enabled this register is updated when the scaler mode register is written LLC Control Register 0 SCW1_0 - 4 0 SCW2_0 - 4 16 16 SCBRI BR 0 LPF2 0 0 48 48 0 CBW2 YLIM16 SCCT CT PFS h'53 0 0 PK PKCOR h'65 vertical freeze start freeze llc pll for llc_start < line number < llc_stop bit[11:0] allowed values from -156...+156 vertical freeze stop freeze llc pll for llc_start < line number < llc_stop bit[11:0] allowed values from -156...+156 20 bit llc clock center frequency 12.27 MHz -79437 = h'FEC9B2 13.5 MHz 174763 = h'02AAAB 14.75 MHz 194181 = h'02F685 16 MHz -135927 = h'FDED08 18 MHz 174763 = h'02AAAB -10 LLC_START h'66 4 LLC_STOP h'69 h'6a 42 = h'02A 2731 = h'AAB LLC_CLOCKH LLC_CLOCKL Micronas 51 VPC 323xD PRELIMINARY DATA SHEET FP Subaddress Function Default Name h'61 pll frequency limiter, 8% 12.27 MHz 30 13.5 MHz 54 14.75 MHz 62 16 MHz 48 18 MHz 54 llc clock generator control word bit[5:0] hardware register shadow llc_clkc = 5AE12.27 MHz llc_clkc = 5AE13.5 MHz llc_clkc = 35AE14.75 MHz llc_clkc = 3AE16 MHz llc_clkc = 3AE18 MHz bit[10:6] reserved bit[11] 0/1 enable/disable llc pll 54 LLC_DFLIMIT h'6d 2053 LLC_CLKC 52 Micronas PRELIMINARY DATA SHEET VPC 323xD 3.2.2. Scaler Adjustment In case of linear scaling, most of the scaler registers need not be set. Only the scaler mode, active video length, and the fixed scaler increments (scinc1/scinc2) must be written. The adjustment of the scaler for nonlinear scaling modes should use the parameters given in table 3-4. An example for `panorama vision' mode with 13.5 MHz line-locked clock is depicted in Fig. 3-2. The figure shows the scaling of the input signal and the variation of the scaling factor during the active video line. The scaling factor starts below 1, i.e. for the borders the video data is expanded by scaler 2. The scaling factor becomes one and compression scaling is done by scaler 1. When the picture center is reached, the scaling factor is held constant. At the second border the scaler increment is inverted and the scaling factor changes back symmetrically. The picture indicates the function of the scaler increments and the scaler window parameters. The correct adjustment requires that pixel counts for the respective windows are always in number of output samples of scaler 1 or 2. 3.2.1. Calculation of Vertical and East-West Deflection Coefficients In Table 3-3 the formula for the calculation of the deflection initialization parameters from the polynominal coefficients a,b,c,d,e is given for the vertical and East-West deflection. Let the polynomial be P / a + b(x - 0.5) + c(x - 0.5)2 + d(x - 0.5)3 + e(x - 0.5)4 The initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for East-West deflection are 12-bit values. The coefficients that should be used to calculate the initialization values for different field frequencies are given below, the values must be scaled by 128, i.e. the value for a0 of the 50 Hz vertical deflection is a0 = (a * 128 - b * 1365.3 + c * 682.7 - d * 682.7) / 128 Table 3-3: Tables for the Calculation of Initialization values for Vertical Sawtooth and East-West Parabola Vertical Deflection 50 Hz a a0 a1 a2 a3 Vertical Deflection 60 Hz a a0 a1 a2 a3 128 b -1365.3 1083.5 c +682.7 -1090.2 429.9 d -682.7 +1645.5 -1305.8 1023.5 a3 a4 125.6 -2046.6 1584.8 a0 a1 a2 a 128 East-West Deflection 50 Hz d -682.7 +1363.4 -898.4 585.9 a0 a1 a2 a3 a4 a 128 b -341.3 111.9 c 1365.3 -899.6 586.8 d -85.3 84.8 -111.1 72.1 e 341.3 -454.5 898.3 -1171.7 756.5 b -1365.3 899.6 c +682.7 -904.3 296.4 128 East-West Deflection 60 Hz b -341.3 134.6 c 1365.3 -1083.5 849.3 d -85.3 102.2 -161.2 e 341.3 -548.4 1305.5 Micronas 53 VPC 323xD PRELIMINARY DATA SHEET border center border input signal video signal output signal scinc compression ratio scinc1 scinc2 expansion (scaler2) scaler window 0 cutpoints 1 compression (scaler1) 1 2 compression (scaler1) 3 expansion (scaler2) 4 Fig. 3-2: Scaler operation for `panorama' mode at 13.5 MHz Table 3-4: Set-up values for nonlinear scaler modes Mode DIGIT3000 (20.25 MHz) `waterglass' border 35% Register scinc1 scinc2 scinc fflim scw1 - 0 scw1 - 1 scw1 - 2 scw1 - 3 scw1 - 4 scw2 - 0 scw2 - 1 scw2 - 2 scw2 - 3 scw2 - 4 center 3/4 1643 1024 90 945 110 156 317 363 473 110 156 384 430 540 center 5/6 1427 1024 56 985 115 166 327 378 493 115 166 374 425 540 `panorama' border 30% center 4/3 1024 376 85 921 83 147 314 378 461 122 186 354 418 540 center 6/5 1024 611 56 983 94 153 339 398 492 118 177 363 422 540 LLC (13.5 MHz) `waterglass' border 35% center 3/4 2464 1024 202 719 104 104 256 256 360 104 104 256 256 360 center 5/6 2125 1024 124 719 111 111 249 249 360 111 111 249 249 360 `panorama' border 30% center 4/3 1024 573 190 681 29 115 226 312 341 38 124 236 322 360 center 6/5 1024 914 126 715 13 117 241 345 358 14 118 242 346 360 54 Micronas PRELIMINARY DATA SHEET VPC 323xD 4. Specifications 4.1. Outline Dimensions 0.17 0.04 64 65 41 40 15 x 0.8 = 12.0 0.1 0.8 17.2 0.15 0.37 0.04 80 1 23.2 0.15 3 0.2 24 25 1.3 0.05 2.7 0.1 0.1 20 0.1 14 0.1 23 x 0.8 = 18.4 0.1 0.8 SPGS705000-3(P80)/1E Fig. 4-1: 80-Pin Plastic Quad Flat Package (PQFP80) Weight approximately 1.61 g Dimensions in mm 4.2. Pin Connections and Short Descriptions NC = not connected LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram SUPPLYA = 4.75...5.25 V, SUPPLYD = 3.15...3.45 V Pin No. PQFP 80-pin Pin Name Type Connection (if not used) Short Description 1 2 3 4 5 6 7 8 9 10 11 12 13 B1/CB1IN G1/Y1IN R1/CR1IN B2/CB2IN G2/Y2IN R2/CR2IN ASGF FFRSTWIN VSUPCAP VSUPD GND D GND CAP SCL IN IN IN IN IN IN VREF VREF VREF VREF VREF VREF X Blue1/Cb1 Analog Component Input Green1/Y1 Analog Component Input Red1/Cr1 Analog Component Input Blue2/Cb2 Analog Component Input Green2/Y2 Analog Component Input Red2/Cr2 Analog Component Input Analog Shield GNDF FIFO Reset Write Input ** Digital Decoupling Circuitry Supply Voltage Supply Voltage, Digital Circuitry Ground, Digital Circuitry Digital Decoupling Circuitry GND I2C Bus Clock IN OUT SUPPLYD SUPPLYD OUT IN/OUT LV or GNDD X X X X X Micronas 55 VPC 323xD PRELIMINARY DATA SHEET Pin No. PQFP 80-pin Pin Name Type Connection (if not used) Short Description 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 SDA RESQ TEST VGAV YCOEQ FFIE FFWE FFRSTW FFRE FFOE CLK20 GNDPA VSUPPA LLC2 LLC1 VSUPLLC GNDLLC Y7 Y6 Y5 Y4 GNDY VSUPY Y3 Y2 Y1 Y0 C7 C6 C5 C4 IN/OUT IN IN IN IN OUT OUT OUT OUT OUT IN/OUT OUT OUT OUT IN/OUT SUPPLYD SUPPLYD OUT OUT OUT OUT SUPPLYD SUPPLYD OUT OUT OUT OUT OUT OUT OUT OUT X X GNDD GNDD GNDD LV LV LV LV LV LV X X LV LV X X GNDY GNDY GNDY GNDY X X GNDY GNDY GNDY GNDY GNDC GNDC GNDC GNDC I2C Bus Data Reset Input, Active Low Test Pin, connect to GNDD VGAV Input Y/C Output Enable Input, Active Low FIFO Input Enable FIFO Write Enable FIFO Reset Write/Read FIFO Read Enable FIFO Output Enable Main Clock Output 20.25 MHz Pad Decoupling Circuitry GND Pad Decoupling Circuitry Supply Voltage Double Clock Output Clock Output Supply Voltage, LLC Circuitry Ground, LLC Circuitry Picture Bus Luma (MSB) Picture Bus Luma Picture Bus Luma Picture Bus Luma Ground, Luma Output Circuitry Supply Voltage, Luma Output Circuitry Picture Bus Luma Picture Bus Luma Picture Bus Luma Picture Bus Luma (LSB) Picture Bus Chroma (MSB) Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma 56 Micronas PRELIMINARY DATA SHEET VPC 323xD Pin No. PQFP 80-pin Pin Name Type Connection (if not used) Short Description 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 62 63 64 65 66 67 68 69 70 71 72 73 74 75 VSUPC GND C C3 C2 C1 C0 GND SY VSUPSY INTLC AVO FSY/HC/HSYA MSY/HS VS FPDAT/VSYA VSTBY CLK5 XTAL1 XTAL2 ASGF GND F VRT I2CSEL ISGND VSUPF VOUT CIN VIN1 VIN2 VIN3 VIN4 SUPPLYD SUPPLYD OUT OUT OUT OUT SUPPLYD SUPPLYD OUT OUT OUT IN/OUT OUT IN/OUT SUPPLYA OUT IN OUT X X GNDC GNDC GNDC GNDC X X LV LV LV LV LV LV X LV X X X Supply Voltage, Chroma Output Circuitry Ground, Chroma Output Circuitry Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma (LSB) Ground, Sync Pad Circuitry Supply Voltage, Sync Pad Circuitry Interlace Output Active Video Output Front Sync/ Horizontal Clamp Pulse/Front-End Horizontal Sync Output ** Main Sync/Horizontal Sync Pulse Vertical Sync Pulse Front-End /Back-End Data/Front-End Vertical Sync Output ** Standby Supply Voltage CCU 5 MHz Clock Output Analog Crystal Input Analog Crystal Output Analog Shield GNDF Ground, Analog Front-End Reference Voltage Top, Analog I2C Bus Address Select Signal Ground for Analog Input, connect to GND F Supply Voltage, Analog Front-End Analog Video Output Chroma / Analog Video 5 Input Video 1 Analog Input Video 2 Analog Input Video 3 Analog Input Video 4 Analog Input SUPPLYA OUTPUT IN SUPPLYA SUPPLYA OUT IN IN IN IN IN X X X X X LV LV* VRT* VRT VRT VRT Micronas 57 VPC 323xD PRELIMINARY DATA SHEET Pin No. PQFP 80-pin Pin Name Type Connection (if not used) Short Description 76 77 78 79 80 61 VSUPAI GNDAI VREF FB1IN AISGND NC SUPPLYA SUPPLYA OUTPUT IN SUPPLYA - X X X VREF X LV OR GNDD Supply Voltage, Analog Component Inputs Front-End Ground, Analog Component Inputs Front-End Reference Voltage Top, Analog Component Inputs Front-End Fast Blank Input Signal Ground for Analog Component Inputs, connect to GNDAI Not connected *) chroma selector must be set to 1 (CIN chroma select) **) available since VPC 323xD-C5 Pin 14- I2C Bus Data SDA (Fig. 4-13) This pin connects to the I2C bus data line. Pin 15 - Reset Input RESQ (Fig. 4-3) A low level on this pin resets the VPC 323xD. Pin 16 - Test Input TEST (Fig. 4-3) This pin enables factory test modes. For normal operation, it must be connected to ground. Pin 17 - VGAV-Input (Fig. 4-3) This pin is connected to the vertical sync signal of a VGA signal. Pin 18 - YC Output Enable Input YCOEQ (Fig. 4-3) A low level on this pin enables the luma and chroma outputs. Pin 19 - FIFO Input Enable FFIE (Fig. 4-4) This pin is connected to the IE pin of the external field memory. Pin 20 - FIFO Write Enable FFWE (Fig. 4-4) This pin is connected to the WE pin of the external field memory. Pin 21 - FIFO Reset Write/Read FFRSTW (Fig. 4-4) This pin is connected to the RSTW pin of the external field memory. Pin 22 - FIFO Read Enable FFRE (Fig. 4-4) This pin is connected to the RE pin of the external field memory. Pin 23 - FIFO Output Enable FFOE (Fig. 4-4) This pin is connected to the OE pin of the external field memory. 4.3. Pin Descriptions (pin numbers for PQFP80 package) Pins 1-3 - Analog Component Inputs RGB1/YCrCb1 (Fig. 4-11) These are analog component inputs with fast blank control. A RGB or YCrCb signal is converted using the component AD converter. The input signals must be AC-coupled. Pins 4-6 - Analog Component Inputs RGB2/YCrCb2 (Fig. 4-11) These are analog component inputs without fastblank control. A RGB or YCrCb signal is converted using the component AD converter. The input signals must be AC-coupled. Pin 7, 64 - Ground, Analog Shield Front-End GNDF Pin 8 - FIFO Reset Write Input FFRSTWIN (Fig. 4-3) In case of a two VPCD application, this pin connects to the FFRSTW pin of the VPCDpip. Pin 9 - Supply Voltage, Decoupling Circuitry VSUPCAP This pin is connected with 220 nF/1.5 nF/390 pF to GNDCAP. Pin 10 - Supply Voltage, Digital Circuitry VSUPD Pin 11 - Ground, Digital Circuitry GNDD Pin 12 - Ground, Decoupling Circuitry GNDCAP Pin 13- I2C Bus Clock SCL (Fig. 4-13) This pin connects to the I2C bus clock line. 58 Micronas PRELIMINARY DATA SHEET VPC 323xD nous to the input signal. The timing is programmable or b) to synchronize an external video horizontally, that is asynchronous to the input video and stored in an external memory. The timing is fixed. In DIGIT3000 mode, this pin supplies the front sync information. Pin 56 - Main Sync/Horizontal Sync Pulse MSY/HS (Fig. 4-4) This pin supplies the horizontal sync pulse information in line-locked mode. In DIGIT3000 mode, this pin is the main sync input. Pin 57 - Vertical Sync Pulse, VS (Fig. 4-4) This pin supplies the vertical sync signal. Pin 58 - Front-End /Back-End Data/Front-End Vertical Sync Output FPDAT/VSYA (Fig. 4-5) In DIGIT3000 mode, this pin interfaces to the DDP 331x back-end processor. The information for the deflection drives and for the white drive control, i. e. the beam current limiter, is transmitted by this pin. In LLC mode, this signal can be used to synchronize an external video vertically, that is asynchronous to the input video and stored in an external memory. The timing is fixed. If not used, this pin is connected with 10k to VSUPSY. Pin 59 - Standby Supply Voltage VSTDBY In standby mode, only the clock oscillator is active, GNDF should be ground reference. Please activate RESQ before powering-up other supplies Pin 60 - CCU 5 MHz Clock Output CLK5 (Fig. 4-10) This pin provides a clock frequency for the TV microcontroller, e.g. a CCU 3000 controller. It is also used by the DDP 331x display controller as a standby clock. Pins 62and 63 - XTAL1 Crystal Input and XTAL2 Crystal Output (Fig. 4-7) These pins are connected to an 20.25 MHz crystal oscillator which is digitally tuned by integrated shunt capacitances. The CLK20 and CLK5 clock signals are derived from this oscillator. An external clock can be fed into XTAL1. In this case, clock frequency adjustment must be switched off. Pin 65 - Ground, Analog Front-End GNDF Pin 24 - Main Clock Output CLK20 (Fig. 4-4) This is the 20.25 MHz main clock output. Pin 25 - Ground, Analog Pad Circuitry GNDPA Pin 26 - Supply Voltage, Analog Pad Circuitry VSUPPA This pin is connected with 47 nF/1.5 nF to GNDPA Pin 27 - Double Output Clock, LLC2 (Fig. 4-4) Pin 28 - Output Clock, LLC1 (Fig. 4-4) This is the clock reference for the luma, chroma, and status outputs. Pin 29 - Supply Voltage, LLC Circuitry VSUPLLC This pin is connected with 68 nF to GNDLLC Pin 30 - Ground, LLC Circuitry GNDLLC Pins 31 to 34, 37 to 40 - Luma Outputs Y7 - Y0 (Fig. 4-4) These output pins carry the digital luminance data. The outputs are clocked with the LLC1 clock. In ITUR656 mode, the Y/C data is multiplexed and clocked with LLC2 clock. Pin 35- Ground, Luma Output Circuitry GNDY This pin is connected with 68 nF to GNDY Pin 36 - Supply Voltage, Luma Output Circuitry VSUPY Pins 41 to 44, 47 to 50 - Chroma Outputs C7-C0 (Fig. 4-4) These outputs carry the digital CrCb chrominance data. The outputs are clocked with the LL1 clock. The CrCb data is sampled at half the clock rate and multiplexed. The CrCb multiplex is reset for each TV line. In ITUR656 mode, the chroma outputs can be tri-stated. Pin 45 - Supply Voltage, Chroma Output Circuitry VSUPC This pin is connected with 68 nF to GNDC Pin 46 - Ground, Chroma Output Circuitry GNDC Pin 51 - Ground, Sync Pad Circuitry GNDSY Pin 52 - Supply Voltage, Sync Pad Circuitry VSUPSY This pin is connected with 47 nF/1.5 nF to GNDSY Pin 53 - Interlace Output, INTLC (Fig. 4-4) This pin supplies the interlace information, 0 indicates first field, 1 indicates second field. Pin 54 - Active Video Output, AVO (Fig. 4-4) This pin indicates the active video output data. The signal is clocked with the LLC1 clock. Pin 55 - Front Sync/Horizontal Clamp Pulse/Front-End Horizontal Sync Output, FSY/HC/HSYA (Fig. 4-4) This signal can be used a) to clamp an external video signal, that is synchro- Pin 66 - Reference Voltage Top VRT (Fig. 4-8) Via this pin, the reference voltage for the A/D converters is decoupled. The pin is connected with 10 F/47 nF to the Signal Ground Pin. Pin 67 - I2C Bus address select I2CSEL (Fig. 4-12) This pin determines the I2C bus address of the IC. Micronas 59 VPC 323xD Table 4-1: VPC 323xD I2C address select I2CSEL GNDF VRT VSUPF I2C Add. 88/89 hex 8C/8D hex 8E/8F hex PRELIMINARY DATA SHEET Pins 72-75 - Video Input 1-4 (Fig. 4-11) These are the analog video inputs. A CVBS or S-VHS luma signal is converted using the luma (Video 1) AD converter. The VIN1 input can also be switched to the chroma (Video 2) ADC. The input signal must be AC-coupled. Pin 76 - Supply Voltage, Analog Component Inputs Front-End VSUPAI This pin is connected with 220 nF/1.5 nF/390 pF to GND AI Pin 77 - Ground, Analog Component Inputs Front-End GND AI Pin 78 - Reference Voltage Top VREF (Fig. 4-8) Via this pin, the reference voltage for the analog component A/D converters is decoupled. The pin is connected with 10 F/47 nF to the Analog Component Signal Ground Pin. Pin 79 - Fast Blank Input FB1IN (Fig. 4-10) This pin is connected to the analog fast blank signal. It controls the insertion of the RGB1/YCrCb1 signals. The input signal must be DC-coupled. Pin 80 - Signal GND for Analog Component Inputs AISGND (Fig. 4-10) This is the high quality ground reference for the component input signals. Pin 68 - Signal GND for Analog Input ISGND (Fig. 4- 10) This is the high quality ground reference for the video input signals. Pin 69 - Supply Voltage, Analog Front-End VSUPF (Fig. 4-8) This pin is connected with 220 nF/1.5 nF/390 pF to GNDF Pin 70 - Analog Video Output, VOUT (Fig. 4-6) The analog video signal that is selected for the main (luma, CVBS) ADC is output at this pin. An emitter follower is required at this pin. Pin 71 - Chroma Input CIN (Fig. 4-9) This pin is connected to the S-VHS chroma signal. A resistive divider is used to bias the input signal to the middle of the converter input range. CIN can only be connected to the chroma (Video 2) A/D converter. The signal must be AC-coupled. 60 Micronas PRELIMINARY DATA SHEET VPC 323xD 4.4. Pin Configuration INTLC AVO FSY/HC/HSYA MSY/HS VS FPDAT/VSYA VSTBY CLK5 NC XTAL1 XTAL2 ASGF VSUPSY GNDSY C0 C1 C2 C3 GNDC VSUPC C4 C5 C6 C7 GNDF VRT I2CSEL ISGND VSUPF VOUT CIN VIN1 VIN2 VIN3 VIN4 VSUPAI GNDAI VREF FB1IN AISGND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 39 38 37 36 35 34 Y0 Y1 Y2 Y3 VSUPY GNDY Y4 Y5 Y6 Y7 GNDLLC VSUPLLC LLC1 LLC2 VSUPPA GNDPA VPC 323xD 33 32 31 30 29 28 27 26 25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 B1/CB1IN G1/Y1IN R1/CR1IN B2/CB2IN G2/Y2IN R2/CR2IN ASGF FFRSTWIN VSUPCAP VSUPD GNDD GNDCAP CLK20 FFOE FFRE FFRSTW FFWE FFIE YCOEQ VGAV TEST RESQ SDA SCL Fig. 4-2: 80-pin PQFP package Micronas 61 VPC 323xD 4.5. Pin Circuits VSUPD 0.5M PRELIMINARY DATA SHEET P P VSTBY N GNDD Fig. 4-3: Input pins RESQ, TEST, VGAV, YCOEQ, FFRSTWRIN - + V SUPD P P V SUPP Vref N f ECLK GNDF Fig. 4-7: Input/Output Pins XTAL1, XTAL2 V SUPF P VRT ADC Reference ISGND N N Fig. 4-8: Pins VRT, ISGND and VREF, AISGND GND P Fig. 4-4: Output pins C0-C7, Y0-Y7, FSY, MSY, HC, AVO, VS, INTLC, HS, LLC1, LLC2, CLK20, FFWE, FFRE, FFIE, FFRD, RSTWR VSUPF To ADC VSUPD P P Fig. 4-9: Chroma input CIN GNDF N N GNDD VSTBY P N GNDF VSUPF P VOUT VREF VSUPF N GNDF To ADC Fig. 4-5: Input/Output pin FPDAT Vin's - + Fig. 4-10: Output pin CLK5 Fig. 4-6: Output pin VOUT GNDF Fig. 4-11: Input pins VIN1-VIN4, RGB/YCrCb1/2, FB1IN 62 Micronas PRELIMINARY DATA SHEET VPC 323xD VSUPF I2CSEL GNDD Fig. 4-13: Pins SDA, SCL VGNDF Fig. 4-12: I2CSEL Micronas 63 VPC 323xD 4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings Symbol TA TS VSUPA/D VI VO Parameter Ambient Operating Temperature Storage Temperature Supply Voltage, all Supply Inputs Input Voltage, all Inputs Output Voltage, all Outputs Pin No. - - Min. 0 -40 -0.3 -0.3 -0.3 PRELIMINARY DATA SHEET Max. 65 125 6 VSUPA+0.3 VSUPD+0.3 Unit C C V V V Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 4.6.2. Recommended Operating Conditions Symbol TA TC VSUP VSUPD fXTAL Parameter Ambient Operating Temperature Case Operating Temperature Supply Voltages, all analog Supply Pins Supply Voltages, all digital Supply Pins Clock Frequency Pin Name - - - - XTAL1/2 Min. 0 0 4.75 3.15 - Typ. - - 5.0 3.3 20.25 Max. 65 105 5.25 3.45 - Unit C C V V MHz 64 Micronas PRELIMINARY DATA SHEET VPC 323xD 4.6.3. Recommended Crystal Characteristics Symbol TA fP fP/fP fP/fP RR C0 C1 Parameter Operating Ambient Temperature Parallel Resonance Frequency with Load Capacitance CL = 13 pF Accuracy of Adjustment Frequency Temperature Drift Series Resistance Shunt Capacitance Motional Capacitance Min. 0 - - - - 3 20 Typ. - 20.250000 - - - - - Max. 65 - 20 30 25 7 30 Unit C MHz ppm ppm pF fF Load Capacitance Recommendation C Lext External Load Capacitance 1) from pins to Ground (pin names: Xtal1 Xtal2) - 3.3 - pF DCO Characteristics 2,3) C ICLoadmin Effective Load Capacitance @ min. DCO-Position, Code 0, package: 68PLCC Effective Load Capacitance Range, DCO Codes from 0..255 3 4.3 5.5 pF C ICLoadrng 1) 11 12.7 15 pF Remarks on defining the External Load Capacitance: External capacitors at each crystal pin to ground are required. They are necessary to tune the effective load capacitance of the PCBs to the required load capacitance CL of the crystal. The higher the capacitors, the lower the clock frequency results. The nominal free running frequency should match fp MHz. Due to different layouts of customer PCBs the matching capacitor size should be determined in the application. The suggested value is a figure based on experience with various PCB layouts. Tuning condition: Code DVCO Register=-720 2) Remarks on Pulling Range of DCO: The pulling range of the DCO is a function of the used crystal and effective load capacitance of the IC (CICLoad +CLoadBoard). The resulting frequency fL with an effective load capacitance of CLeff = CICLoad + C LoadBoard is: 1 + 0.5 * [ C1 / (C0 + CL) ] fL = fP * _______________________ 1 + 0.5 * [ C1 / (C0 + CLeff) ] 3) Remarks on DCO codes The DCO hardware register has 8 bits, the FP control register uses a range of -2048...2047 Micronas 65 VPC 323xD 4.6.4. Characteristics PRELIMINARY DATA SHEET at TA = 0 to 65 C, VSUPF = 4.75 to 5.25 V, VSUPD = 3.15 to 3.45 V, f = 20.25 MHz for min./max. values at TC = 60 C, VSUPF = 5 V, VSUPD = 3.3 V, f = 20.25 MHz for typical values Symbol PTOT IVSUPA IVSUPD IVSTDBY IL Parameter Total Power Dissipation Current Consumption Current Consumption Current Consumption Input / Output Leakage Current VSUPF VSUPD VSTDBY All I/O Pins Pin Name Min. - - - - -1 Typ. 720 75 102 1 - Max. 1000 100 140 - 1 Unit mW mA mA mA A 4.6.4.1. Characteristics, 5 MHz Clock Output Symbol VOL VOH tOT Parameter Output Low Voltage Output High Voltage Pin Name CLK5 Min. - 4.0 Typ. - - Max. 0.4 V- STDBY - Unit V V Test Conditions IOL = 0.4 mA -IOL = 0.9 mA CLOAD = 30 pF Output Transition Time - 50 ns 4.6.4.2. Characteristics, 20 MHz Clock Input/Output, External Clock Input (XTAL1) Symbol VDCAV VPP tOT VIT VI Parameter DC Average Pin Name CLK20 Min. VSUPD/2 - 0.3 VSUPD/2 - 0.3 - 2.1 XTAL1 1.3 Typ. V SUPD/2 V SUPD/2 - 2.5 - Max. VSUPD/2 + 0.3 VSUPD/2 + 0.3 18 2.9 - Unit V Test Conditions CLOAD = 30 pF CLOAD = 30 pF CLOAD = 30 pF only for test purposes capacitive coupling used, XTAL2 open VOUT Peak to Peak Output Transition Time Input Trigger Level Clock Input Voltage V ns V VPP 4.6.4.3. Characteristics, Reset Input, Test Input, VGAV Input, YCOEQ Input Symbol VIL VIH tOEED Parameter Input Low Voltage Input High Voltage Data Output Enable/Disable Time Pin Name RESQ TEST VGAV YCOEQ YCOEQ Min. - 2.0 12 Typ. - - - Max. 0.8 - 15 Unit V V ns Test Conditions 66 Micronas PRELIMINARY DATA SHEET VPC 323xD 4.6.4.4. Characteristics, Power-up Sequence Symbol tVdel tVrmpl Parameter Ramp Up Difference of Supplies Transition Time of Supplies Pin Name Min. -1 - Typ. - - Max. 1 50 Unit s ms Test Conditions tVrmp 0.9 * VSUPAI VSUPF time / ms tVdel 0.9 * VSUPD VSTBY time / ms max. 1ms LLC (maximum guaranteed start-up time) time / ms RESQ 0.8 * VSUPD min. 1ms time / ms max. 0.05ms SDA/SCL I2C-cycles invalid time / ms Fig. 4-14: Power-Up sequence Micronas 67 VPC 323xD 4.6.4.5. Characteristics, FPDAT Input/Output Symbol VOL tOH tODL VIL V IH tIS tIH CL Parameter Output Low Voltage Output Hold Time Output Delay Time Input Low Voltage Input High Voltage Input Setup Time Input Hold Time Load capacitance Pin Name FPDAT Min. - 6 - - 1.5 7 5 - Typ. - - - - - - - - Max. 0.5 - 35 0.8 - - - 40 PRELIMINARY DATA SHEET Unit V ns ns V V ns ns pF Test Conditions IOL = 4.0 mA CL = 40 pF 4.6.4.6. Characteristics, I2C Bus Interface Symbol VIL V IH V OL VIH tF tR fSCL tLOW tHIGH tSU Data tHD Data Parameter Input Low Voltage Input High Voltage Output Low Voltage Pin Name SDA, SCL Min. - 2.0 - Typ. - - - Max. 1.0 - 0.4 0.6 5 300 300 400 - - - 0.9 Unit V V V V pF ns ns kHz s s ns s CL = 400 pF CL = 400 pF Il = 3 mA Il = 6 mA Test Conditions Input Capacitance Signal Fall Time Signal Rise Time Clock Frequency Low Period of SCL High Period of SCL Data Set Up Time to SCL high DATA Hold Time to SCL low SDA SCL - - - 0 1.3 0.6 100 0 - - - - - - - - 4.6.4.7. Characteristics, I2C Bus Address Select I2CSEL Input Symbol VIL VIH VMED Parameter Input Low Voltage Input High Voltage Input Medium Voltage Pin Name I2CSEL Min. GNDF 3.7 VRT Typ. - - - Max. 1.3 VSUPF VRT Unit V V V Test Conditions 68 Micronas PRELIMINARY DATA SHEET VPC 323xD 4.6.4.8. Characteristics, Analog Video and Component Inputs Symbol VVIN Parameter Analog Input Voltage Pin Name VIN1, VIN2 VIN3, VIN4 CIN R1/CR1IN G1/Y1IN B1/CB1IN R2/CR2IN G2/Y2IN B2/CB2IN FBIN VIN1, VIN2 VIN3, VIN4 CIN Min. 0 Typ. - Max. 3.5 Unit V Test Conditions CCP CCP CCP Input Coupling Capacitor Video Inputs Input Coupling Capacitor Chroma Input Input Coupling Capacitor Component Input - 680 - nF - 1 - nF R1/CR1IN G1/Y1IN B1/CB1IN R2/CR2IN G2/Y2IN B2/CB2IN - 220 - nF 4.6.4.9. Characteristics, Analog Front-End and ADCs Symbol VVRT Luma - Path RVIN CVIN V VIN VVIN AGC DNLAGC V VINCL QCL ICL-LSB DNLICL Input Resistance Input Capacitance Full Scale Input Voltage Full Scale Input Voltage AGC step width AGC Differential Non-Linearity Input Clamping Level, CVBS VIN1 VIN2 VIN3 VIN4 VIN1 VIN2 VIN3 VIN4 VIN1 VIN2 VIN3 VIN4 1 - 1.8 0.5 - - - 1.0 - - 2.0 0.6 0.166 - 4.5 2.2 0.7 - 0.5 - M pF VPP VPP dB LSB V min. AGC Gain max. AGC Gain 6-Bit Resolution= 64 Steps fsig=1MHz, - 2 dBr of max. AGC-Gain Binary Level = 64 LSB min. AGC Gain 5 Bit - I-DAC, bipolar VVIN =1.5 V Code Clamp-DAC=0 Parameter Reference Voltage Top Pin Name VRT VREF Min. 2.4 Typ. 2.5 Max. 2.6 Unit V Test Conditions 10 F/10 nF, 1 G Probe Clamping DAC Resolution Input Clamping Current per step Clamping DAC Differential NonLinearity -16 0.7 - - 1.0 - 15 1.3 0.5 steps A LSB Micronas 69 VPC 323xD PRELIMINARY DATA SHEET Symbol Chroma - Path RCIN VCIN V CINDC Parameter Pin Name Min. Typ. Max. Unit Test Conditions Input Resistance SVHS Chroma Full Scale Input Voltage, Chroma Input Bias Level, SVHS Chroma Binary Code for Open Chroma Input CIN VIN1 1.4 2.0 2.6 k 1.08 1.2 1.32 VPP V - 1.5 - - 128 - - Component - Path RVIN CVIN V VIN VVIN VVINCL V VINCL Input Resistance Input Capacitance Full Scale Input Voltage Full Scale Input Voltage Input Clamping Level RGB, Y R1/CR1IN G1/Y1IN B1/CB1IN R2/CR2IN G2/Y2IN B2/CB2IN 1 - 0.85 1.2 - - - 1.0 1.4 1.06 - 4.5 1.1 1.6 - M pF VPP VPP V min. Gain (XAR=-0) max. Gain (XAR=-1) Binary Level = 16 LSB XAR=-0 Binary Level = 128 LSB XAR=-0 Full Scale at 1 MHz, XAR=-0 6 Bit - I-DAC, bipolar VVIN =1.5 V Code Clamp-DAC=0 Input Clamping Level Cr, Cb - 1.5 - V Gain Match QCL ICL-LSB DNLICL Clamping DAC Resolution Input Clamping Current per step Clamping DAC Differential NonLinearity - -32 0.59 - 1.2 - 0.85 - 1.7 31 1.11 0.5 % steps A LSB Dynamic Characteristics for all Video-Paths (Luma + Chroma) and Component-Paths BW XTALK THD Bandwidth Crosstalk, any Two Video Inputs Total Harmonic Distortion VIN1 VIN2 VIN3 VIN4 R1/CR1IN G1/Y1IN B1/CB1IN R2/CR2IN G2/Y2IN B2/CB2IN 8 - - 10 -56 -50 - -46 -42 MHz dB dB -2 dBr input signal level 1 MHz, -2 dBr signal level 1 MHz, 5 harmonics, -2 dBr signal level 1 MHz, all outputs, -2 dBr signal level Code Density, DC-ramp SINAD Signal to Noise and Distortion Ratio Integral Non-Linearity Differential Non-Linearity Differential Gain Differential Phase 40 45 - 1 0.8 3 1.5 dB INL DNL DG DP - - - - - - - - LSB LSB % deg -12 dBr, 4.4 MHz signal on DC-ramp 70 Micronas PRELIMINARY DATA SHEET VPC 323xD Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Analog Video Output V OUT AGCVOUT DNLAGC V OUTDC BW Output Voltage AGC step width, VOUT AGC Differential Non-Linearity DC-level VOUT Bandwidth Out: VOUT In: VIN1 VIN2 VIN3 VIN4 1.7 - - - 8 2.0 1.333 - 1 10 2.3 - 0.5 - - VPP dB LSB V MHz clamped to Back porch Input: -2 dBr of main ADC range, CL10 pF Input: -2 dBr of main ADC range, CL10 pF 1 MHz, 5 Harmonics VIN = 1 VPP, AGC= 0 dB 3 Bit Resolution=7 Steps 3 MSBs of main AGC THD VOUT Total Harmonic Distortion - - -40 dB CLVOUT ILVOUT Load Capacitance Output Current VOUT - - - - 10 0.1 pF mA 4.6.4.10.Characteristics, Analog FB Input Symbol RFBIN V FBIN V THFBMO BWFBIN THDFBIN Parameter Input Resistance Full Scale Input Voltage Threshold for FB-Monitor Bandwidth Total Harmonic Distortion Pin Name FB1IN Min. 1 0.85 0.5 8 - Typ. - 1.0 0.65 10 -50 -40 Max. - 1.1 0.8 Unit M VPP VPP MHz dB -2 dBr input signal level 1 MHz, 5 harmonics, -2 dBr signal level 1 MHz, all outputs, -2 dBr signal level Code Density, DC-ramp Test Conditions Code Clamp-DAC=0 SINADFBIN INLFBIN DNLFBIN Signal to Noise and Distortion Ratio Integral Non-Linearity Differential Non-Linearity 34 37 - 1 0.8 dB - - 0.3 0.2 LSB LSB Micronas 71 VPC 323xD 4.6.4.11.Characteristics, Output Pin Specification PRELIMINARY DATA SHEET Output Specification for SYNC, CONTROL, and DATA Pins: Y[7:0], C[7:0], AVO, HS, HC, INTLC, VS, FSY, FFIE, FFWE, FFOE, FFRD, FFRSTWR Symbol CL V OL VOH tOH tOD tOH tOD tOD tOD Parameter Load Capacitance Output Low Voltage Output High Voltage Output Hold Time Pin Name Min. - - 2.4 16 Typ. - - - - Max. 50 0.4 - - Unit pF V V ns Cload =50pF Cload =50pF LLC2=27.0MHz, OMODE=1 DBCLK=0/1 LLC2=27.0MHz, OMODE=1, DBCLK=0/1, NOTE1 LLC2=32.0MHz, OMODE=1, DBCLK=0/1 LLC2=32.0MHz, OMODE=1, DBCLK=0/1, NOTE1 CLK20=20.25MHz, OMODE=0, NOTE1 CLK20=20.25MHz, OMODE=0, NOTE1 Test Conditions Output Delay Time - - 26 ns Output Hold Time 16 - - ns Output Delay Time - - 22 ns Output Hold Time 15 - - ns Output Delay Time - - 35 ns NOTE 1: CLOAD depends on the selected driver strength which is I2C-programable. Table 4-1: Adjustable driver strength for AVO, HS, HC, INTLC, VS, FFIE, FFWE, FFOE, FFRD, FFRSTWR: Strength 0000 0001 0010 0011 0100 0101 0110 0111 Load < 50 pF < 47,5pF < 45,0 pF < 42,5 pF < 40,0pF < 37,5 pF < 35,0 pF < 32,5 pF Strength 1000 1001 1010 1011 1100 1101 1110 1111 Load < 30,0pF < 27,5 pF < 25,0 pF < 22,5 pF < 20,0pF < 17,5pF < 15,0 pF < 12,5 pF 72 Micronas PRELIMINARY DATA SHEET VPC 323xD CLK20 20.25 MHz in case of DIGIT3000 mode LLC2 in case of LLC Mode LLC1 in case of LLC Mode VOH VOL VOH Output Data valid tOH tOD Data valid VOL Fig. 4-15: Sync, control, and data outputs write address point disable N N+1 N+2 N+3 N+4 N+5 disable N+6 N+7 N+8 N+9 N+10 N+11 disable SWCK FFWE FFIE D0-D11 N+1 N+2 N+7 N+8 Fig. 4-16: Field memory write cycle timing Micronas 73 VPC 323xD PRELIMINARY DATA SHEET read address point disable N N+1 N+2 N+3 N+4 N+5 disable N+6 N+7 N+8 N+9 N+10 N+11 disable SRCK FFRE FFOE D0-D11 Hi-z N+1 N+2 Hi-z N+7 N+8 Hi-z Fig. 4-17: Field memory read cycle timing 74 Micronas PRELIMINARY DATA SHEET VPC 323xD 4.6.4.12.Characteristics, Input Pin Specification Input Specification for SYNC, CONTROL, and DATA Pin: MSY (DIGIT3000 mode only) Symbol VIL V IH tIS tIH Parameter Input Low Voltage Input High Voltage Input Setup Time Input Hold Time Pin Name Min. - 1.5 7 5 Typ. - - - - Max. 0.8 - - - Unit V V ns ns Test Conditions CLK20 20.25 MHz in case of DIGIT3000 Mode VIH Input tIS Data valid tIH VIL 2.0 V tR, tF 5ns 0.8 V VIH LLC1 13.5 MHz in case of LLC Mode Input tIS Data valid tIH VIL Fig. 4-18: Sync, control, and data inputs Micronas 75 VPC 323xD 4.6.4.13.Characteristics, Clock Output Specification Line-Locked Clock Pins: LLC1, LLC2 Symbol CL V OL VOH Parameter Load capacitance Output Low Voltage Output High Voltage Pin Name LLC1, LLC2 LLC1, LLC2 LLC1, LLC2 Min. - - 2.4 Typ. - - - Max. 50 0.4 - PRELIMINARY DATA SHEET Unit pF V V Test Conditions IL = 2 mA IH = -2 mA 13.5 MHz Line Locked Clock 1/T1 tWL1 tWH1 tR1, tF1 1/T2 tWL2 tWH2 tR2, tF2 LLC1 Clock Frequency LLC1 Clock Low Time LLC1 Clock High Time Clock Rise/Fall Time Clock LLC2 Clock Frequency LLC2 Clock Low Time LLC2 Clock High Time Clock Rise/Fall TimeClock LLC1 LLC1 LLC1 LLC1 LLC2 LLC2 LLC2 LLC2 12.5 25 25 - 25 5 10 - - - - - - - - - 14.5 - - 5 29 - - 8 MHz ns ns ns MHz ns ns ns CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF 16 MHz Line Locked Clock 1/T1 tWL1 tWH1 tR1, tF1 1/T2 tWL2 tWH2 tR2, tF2 LLC1 Clock Frequency LLC1 Clock Low Time LLC1 Clock High Time Clock Rise/Fall TimeClock LLC2 Clock Frequency LLC2 Clock Low Time LLC2 Clock High Time Clock Rise/Fall TimeClock LLC1 LLC1 LLC1 LLC1 LLC2 LLC2 LLC2 LLC2 14.8 21 21 - 29.6 4 9 - - - - - - - - - 17.2 - - 5 34.4 - - 8 MHz ns ns ns MHz ns ns ns CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF common timings - all modes tSKS Clock Skew 0 - 4 ns LLC1=13.5MHz, LLC2=27MHz 76 Micronas PRELIMINARY DATA SHEET VPC 323xD T13 tWH13 tWL13 LLC1 (13.5 MHz 7%) tR tWH27 tWL27 tF tSK T27 tSK VOH VOL LLC2 (27 MHz 7%) tR tF VOH VOL Fig. 4-19: Line-locked clock output pins Micronas 77 VPC 323xD 5. Application Circuit PRELIMINARY DATA SHEET 78 VPC 323xD Micronas PRELIMINARY DATA SHEET VPC 323xD 5.1. Application Note: VGA mode with VPC 323xD In 100-Hz TV applications it can be desirable to display a VGA-signal on the TV. In this case, a VGA-graphic card delivers the H, V, and RGB signals. These signals are fed "directly" to the back-end signal processing. The VPC generates a stable line-locked clock for the 100-Hz system in relation to the VGA sync signals. While the V-sync is connected to the VGAV pin directly, the H-sync has to be pulse-shaped and amplitude adjusted until it is connected to one of the video input pins of the VPC. The recommended circuitry to filter the H sync is given in the figure below. +5V analog 47pF 1k 270 H 31kHz 540 BC848B 1N4148 2k 1N4148 GND analog GND analog 100 680 nF Video Input VPC Fig. 5-1: Application circuit for horizontal VGA-input Micronas 79 VPC 323xD 5.2. Application Note: PIP Mode Programming 5.2.1. Procedure to Program a PIP Mode For the VPCpip or VPCsingle: 1. set the scaler according to the PIP size to be used (see Table 2-11). 2. write the registers VPCMODE and PIPMODE according to the mode to be set. 3. in expert mode write the registers NLIN, NPIX and NPFB. 4. write the registers COLBGD, COLFR1, COLFR2, HSTR and VSTR, if a different value as the default one is used. 5. write the registers LINOFFS and PIXOFFS, if a different value as the default one or more than 4 inset pictures in the X or Y direction are used. 6. write the register PIPOPER to fill the frame and background of an inset picture. This step is repeated for all inset pictures in a multi PIP application. For the VPCmain: 7. set the scaler to get a full size video (see Table 2-11). 8. write the registers VPCMODE and PIPMODE according to the mode to be set. 9. in expert mode write the registers NLIN, NPIX and NPFB. 10. write the registers COLBGD, HSTR and VSTR, if a different value as the default one is used. 11. write the register PIPOPER to start displaying PIP. Table 5-1: I2C register programing for PIP control I2C register VPCMODE, PIPMODE, PIPOPER COLBGD, COLFR1, COLFR2, HSTR, VSTR LINOFFS, PIXOFFS should be written always update PRELIMINARY DATA SHEET For the VPCpip or VPCsingle: 12. write the register PIPOPER to start filling a inset picture with live video. 13. Only for tuner scanning: write the register PIPOPER to stop filling a inset picture with live video and changing the channel. 14. repeat steps 12 and 13 for all inset pictures in a multi PIP application. 15. Only for VPCsingle: write the register PIPOPER to start filling the main picture part outside the inset picture(s) with live video. For the VPCmain: 16. write the registers HSTR and VSTR, if the PIP position should be changed. 17. write the register PIPOPER, to quit the PIP mode. In an application with a single VPC, step 7 - 11 and 16 - 17 are dropped. Additionally, the free running mode should be set in the cases shown in Table 2-14. 5.2.2. I2C Registers Programming for PIP Control To program a PIP mode, the register VPCMODE, PIPMODE and PIPOPER should be written always, all other registers are used only in the expert mode or if the default values are modified (see Table 5-1). should be written only, if the default values have to be modified VPC pip only used in expert mode, when more than 4 inset pictures in the X or Y direction are used. VPCmain not used. VPCsingle only used if a different value as the default one or more than 4 inset pictures in the X or Y direction are used NLIN, NPIX, NPFB should be written, only in the expert mode. (In the predefined modes the default values are used.) 80 Micronas PRELIMINARY DATA SHEET VPC 323xD Table 5-2: Limits of the I2C register settings for programming a PIP mode I2C register NPFB NPIX NLIN HSTR VSTR PIXOFFS LINOFFS VPCmain VPCpip and VPCsingle NPFB NPIXmain + X, (X=2 for TI and X=0 for other field memories) and NPFB x NLINmain total field memory size 0 < NPIX NPFB - X and 0 < NPIX NPELfp NPFB x NLIN total field memory size and 0 NLIN < NROWfp 0 4 * HSTR< NPELfp - 4 * NPIXmain 0 VSTR < NROWfp - NLINmain not used not used 0 < NPIX NPELsp 0 NLIN < NROWsp 0 HSTR < NPELsp - NPIXPIP 0 VSTR < NROWsp - NLINPIP 0 PIXOFFS < NPIXmain - (number of pixels of inset pictures to the right of PIXOFFS) 0 LINOFFS < NLINmain - (number of lines of inset pictures below LINOFFS) Notes: - NPIXmain and NLINmain: correspond to VPCmain - NPIXPIP and NLIN PIP: correspond to VPCsingle and VPCpip - NROWfp and NPELfp: number of lines per field and number of pixels per line of a full picture (e.g. NROWfp=288, NPELfp= 720 for PAL at 13.5 MHz) - NROWsp and NPELsp: number of lines per field and number of pixels per line of a inset picture The limits of the I2C register settings are given in Table 5-2. No range check and value limitation are carried out in the field memory controller. An illegal setting of these parameters leads to a error behavior of the PIP function. The PIP display is controlled by the commands written into the register PIPOPER. For the VPCmain, the PIP display is turned on or off by the commends DISSTART and DISSTOP. For the VPC pip and VPCsingle, 8 commands are available: - WRFRCOL1, WRFRCOL2: to fill the frame of a inset picture with the color COLFR1 or COLFR2, - WRBGD, WRBGDNF: to fill a inset picture with the background color COLBGD, - WRPIC, WRPICNF, WRSTOP: to start and stop to write a inset picture with the active video, - WRMAIN: to start write the main picture part outside the inset picture(s) with the active video (only for VPCsingle). While WRPIC, WRSTOP, WRFRCOL1, WRFRCOL2 and WRBGD control a display with a frame (see Fig. 5-2), WRPICNF and WRBGDNF control a display without a frame (see Fig. 5-3). The number of the inset picture addressed by the current commend is given by bits NSPX and NSPY in the register PIPOPER. In the display window, the coordinate of the upper-left corner of the inset picture with NSPX=0 and NSPY=0 is defined by the registers LINOFFS and PIXOFFS. If maximal 4x4 inset pictures are used, no new setting of these registers is needed. The default setting LINOFFS=0 and PIXOFFS=0 takes effect. If more than 4x4 inset pictures are involved in a PIP application, these inset pictures should be grouped, so that the inset pictures in each group can be addressed by bits NSPX and NSPY. For writing each group, the registers LINOFFS and PIXOFFS should be set correctly (see Fig.5-4). (LINOFFS, PIXOFFS) 00 00 01 NSPY 10 11 01 NSPX 10 11 display window Fig. 5-2: 4x4 inset pictures with frame Micronas 81 VPC 323xD PRELIMINARY DATA SHEET 5.2.3.2. Select a Strobe Effect in Expert Mode (LINOFFS, PIXOFFS) 00 00 01 NSPY 10 11 01 NSPX 10 11 P1 P2 P3 P4 P5 P6 LINOFFS display window Fig. 5-3: 4x4 inset pictures without frame Fig. 5-4: Example of the expert mode 5.2.3. Examples 5.2.3.1. Select Predefined Mode 2 Scaler settings for VPCpip: SCINC1 = h'480 FFLIM = h'78 NEWLIN = h'194 AVSTRT = h'86 AVSTOP = h'356 SC_PIP = h'1f SC_BRI = h'310 SC_CT = h'30 SC_MODE = h'00 (for S411=0) Scaler settings for VPCpip: SCINC1 = h'600 FFLIM = h'168 NEWLIN = h'194 AVSTRT = h'86 AVSTOP = h'356 SC_PIP = h'11 SC_BRI = h'110 SC_CT = h'30 SC_MODE = h'00 (for S411=0) PIP controller settings to show a strobe effect: For the VPCpip: VPCMODE = h'01 PIPMODE = h'0f VSTR = h'202 HSTR = h'101 NPIX = h'1c NLIN = h'2c NPFB = h'132 PIPOPER = h'c0 (write the background of P1) wait until NEWCMD = 0 PIPOPER = h'a0 (write the frame of P1) wait until NEWCMD = 0 PIPOPER = h'80 (start writing PIP of P1) wait until NEWCMD = 0 PIPOPER = h'c4 (write the background of P2) wait until NEWCMD = 0 PIPOPER = h'a4 (write the frame of P2) wait until NEWCMD = 0 PIPOPER = h'84 (start writing PIP of P2) wait until NEWCMD = 0 PIPOPER = h'c8 (write the background of P3) wait until NEWCMD = 0 PIPOPER = h'a8 (write the frame of P3) wait until NEWCMD = 0 PIPOPER = h'88 (start writing PIP of P3) PIP controller settings to start PIP display: For the VPCpip: VPCMODE = h'01 PIPMODE = h'02 PIPOPER = h'c0 (write the background) wait until NEWCMD = 0 PIPOPER = h'a0 (write the frame) wait until NEWCMD = 0 PIPOPER = h'80 (start writing PIP) After that the PIP position can be changed via HSTR and VSTR registers. e.g. HSTR = h'03 For the VPCmain: VPCMODE = h'05 PIPMODE = h'02 PIPOPER = h'80 (start display PIP) PIP controller settings to stop PIP display: For the VPCmain: PIPOPER = h'90 (stop display PIP) 82 Micronas PRELIMINARY DATA SHEET VPC 323xD PIPMODE = h'06 PIPOPER = h'c0 (write the background of P1) wait until NEWCMD = 0 PIPOPER = h'a0 (write the frame of P1) wait until NEWCMD = 0 PIPOPER = h'c1 (write the background of P2) wait until NEWCMD = 0 PIPOPER = h'a1 (write the frame of P2) wait until NEWCMD = 0 PIPOPER = h'c4 (write the background of P3) wait until NEWCMD = 0 PIPOPER = h'a4 (write the frame of P3) wait until NEWCMD = 0 PIPOPER = h'c5 (write the background of P4) wait until NEWCMD = 0 PIPOPER = h'a5 (write the frame of P4) wait until NEWCMD = 0 wait until NEWCMD = 0 PIPOPER = h'cc (write the background of P4) wait until NEWCMD = 0 PIPOPER = h'ac (write the frame of P4) wait until NEWCMD = 0 PIPOPER = h'8c (start writing PIP of P4) wait until NEWCMD = 0 LINOFFS = h'2b8 PIPOPER = h'c0 (write the background of P5) wait until NEWCMD = 0 PIPOPER = h'a0 (write the frame of P5) wait until NEWCMD = 0 PIPOPER = h'80 (start writing PIP of P5) wait until NEWCMD = 0 PIPOPER = h'c4 (write the background of P6) wait until NEWCMD = 0 PIPOPER = h'a4 (write the frame of P6) wait until NEWCMD = 0 PIPOPER = h'84 (start writing PIP of P6) For the VPCmain: VPCMODE = h'05 PIPMODE = h'0f VSTR = h'201 HSTR = h'193 NPIX = h'1e NLIN = h'116 NPFB = h'132 PIPOPER = h'80 (start display PIP) PIP controller settings to stop PIP display: For the VPCmain: PIPOPER = h'90 (stop display PIP) For the VPCmain: VPCMODE = h'05 PIPMODE = h'46 PIPOPER = h'80 (start display multi PIP) For the VPCpip: tune a channel PIPOPER = h'80 (start writing PIP of P1) wait until NEWCMD = 0 PIPOPER = h'90 (stop writing PIP of P1) wait until NEWCMD = 0 tune an other channel PIPOPER = h'81 (start writing PIP of P2) wait until NEWCMD = 0 PIPOPER = h'91 (stop writing PIP of P2) wait until NEWCMD = 0 tune an other channel PIPOPER = h'84 (start writing PIP of P3) wait until NEWCMD = 0 PIPOPER = h'94 (stop writing PIP of P3) wait until NEWCMD = 0 tune an other channel PIPOPER = h'85 (start writing PIP of P4) wait until NEWCMD = 0 PIPOPER = h'95 (stop writing PIP of P4) wait until NEWCMD = 0 The tuning and writing of the four inset pictures are repeated. 5.2.3.3. Select Predefined Mode 6 for Tuner Scanning Scaler settings for VPCpip: SCINC1 = h'600 FFLIM = h'168 NEWLIN = h'194 AVSTRT = h'86 AVSTOP = h'356 SC_PIP = h'11 SC_BRI = h'110 SC_CT = h'30 SC_MODE = h'00 (for S411=0) PIP controller settings to stop tuner scanning: PIP controller settings for tuner scanning: For the VPCpip: VPCMODE = h'01 For the VPCmain: PIPOPER = h'90 (stop display PIP) Micronas 83 VPC 323xD 6. Data Sheet History 1. Preliminary data sheet: "VPC 323XD Comb Filter Video Processor", July 26, 2001, 6251-472-1PD. First release of the preliminary data sheet. Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-472-1PD All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. 84 Micronas |
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